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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 20002 rev: b amendment/ 0 issue date: february 1997 am186 tm es/eslv and am188 tm es/eslv high performance, 80c186-/80c188-compatible and 80l186-/80l188-compatible, 16-bit embedded microcontrollers distinctive characteristics n e86 ? family 80c186-/188- and 80l186-/188- compatible microcontrollers with enhanced bus interface lower system cost with higher performance 3.3-v 0.3-v operation (am186eslv and am188eslv microcontrollers) n high performance 20-, 25-, 33-, and 40-mhz operating frequencies supports zero-wait-state operation at 25 mhz with 100-ns static memory (am186eslv and am188eslv microcontrollers) and 40 mhz with 70-ns static memory (am186es and am188es microcontrollers) 1-mbyte memory address space 64-kbyte i/o space n enhanced features provide improved memory access and remove the requirement for a 2x clock input nonmultiplexed address bus processor operates at the clock input frequency on the am186es/eslv microcontroller, 8-bit or 16-bit memory and i/o static bus option n enhanced integrated peripherals provide increased functionality, while reducing system cost thirty-two programmable i/o (pio) pins two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers serial port hardware handshaking with cts , rts , enrx , and rtr selectable for each port multidrop 9-bit serial port protocol independent serial port baud rate generators dma to and from the serial ports watchdog timer can generate nmi or reset a pulse-width demodulation option a data strobe, true asynchronous bus interface option included for den pseudo static ram (psram) controller includes auto refresh capability reset configuration register n familiar 80c186/80l186 peripherals two independent dma channels programmable interrupt controller with up to eight external and eight internal interrupts three programmable 16-bit timers programmable memory and peripheral chip-select logic programmable wait state generator power-save clock divider n software-compatible with the 80c186/80l186 and 80c188/80l188 microcontrollers with widely available native development tools, applications, and system software n a compatible evolution of the am186 ? em and am188 ? em microcontrollers n available in the following packages: 100-pin, thin quad flat pack (tqfp) 100-pin, plastic quad flat pack (pqfp) general description the am186 ? es/eslv and am188 ? es/eslv microcontrollers are an ideal upgrade for 80c186/188 and 80l186/188 microcontroller designs requiring 80c186/188 and 80l186/188 compatibility, increased performance, serial communications, and a direct bus interface. the am186es/eslv and am188es/eslv microcontrollers are part of the amd e86 family of embedded microcontrollers and microprocessors based on the x86 architecture. the e86 family includes the 16- and 32-bit microcontrollers and microprocessors described on page 8. the am186es/eslv and am188es/eslv microcontrollers have been designed to meet the most common requirements of embedded products developed for the office automation, mass storage, and communications markets. specific applications include disk drives, hand-held and desktop terminals, set-top controllers, fax machines, printers, photocopiers, feature phones, cellular phones, pbxs, multiplexers, modems, and industrial controls.
2 am186/188es and am186/188eslv microcontrollers preliminary am186es microcontroller block diagram notes: *all pio signals are shared with other physical pins. see the pin descriptions beginning on page 27 and table 2 on page 34 for information on shared functions. ** pwd, int5, int6, rts 1/rtr 1, and cts 1/enrx 1 are multiplexed with int2/inta 0, drq0, drq1, pcs 3, and pcs 2 respec- tively. see the pin descriptions beginning on page 27. s 2Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int6Cint4** int3/inta 1/irq int2/inta 0** int1/select int0 tmrout0 tmrout1 drq0** drq1** v cc gnd tmrin0 tmrin1 ardy srdy dt/r den /ds hold hlda asynchronous serial port 0 txd0 rxd0 nmi a19Ca0 ad15Cad0 ale bhe /aden wr wlb whb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0** pcs 5/a1 ucs /once 1 x2 x1 psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers s6/lock / uzi clkdiv 2 txd1 rxd1 cts 0/enrx 0 cts 1/enrx 1** rts 0/rtr 0 rts 1/rtr 1** watchdog timer (wdt) pulse width demod- ulator (pwd) pwd** asynchronous serial port 1
am186/188es and am186/188eslv microcontrollers 3 preliminary am188es microcontroller block diagram notes: *all pio signals are shared with other physical pins. see the pin descriptions beginning on page 27 and table 2 on page 34 for information on shared functions. ** pwd, int5, int6, rts 1/rtr 1, and cts 1/enrx 1 are multiplexed with int2/inta 0, drq0, drq1, pcs 3, and pcs 2 respec- tively. see the pin descriptions beginning on page 27. interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int6Cint4** int3/inta 1/irq int2/inta 0** int1/select int0 tmrout0 tmrout1 drq0** drq1** tmrin0 tmrin1 asynchronous serial port 0 txd0 rxd0 nmi a19Ca0 ad7Cad0 ale rfsh 2/aden wr wb rd lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0** pcs 5/a1 ucs /once 1 x2 x1 psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers txd1 rxd1 cts 0/enrx 0 cts 1/enrx 1** rts 0/rtr 0 rts 1/rtr 1** watchdog timer (wdt) pulse width demod- ulator (pwd) pwd** asynchronous serial port 1 s 2Cs 0 v cc gnd ardy srdy dt/r den /ds hold hlda res s6/lock / uzi clkdiv 2 ao15Cao8
4 am186/188es and am186/188eslv microcontrollers preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. -40 am186es C20 = 20 mhz C25 = 25 mhz C33 = 33 mhz C40 = 40 mhz c temperature range c=es commercial (t c =0 c to +100 c) speed option device number/description \w lead forming \w=trimmed and formed valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: the industrial version of the am186es and am188es microcontrollers, as well as the am186eslv and am188eslv, are available in 20 and 25 mhz operating frequencies only. the am186es, am188es, am186eslv, and am188eslv microcontrollers are all functionally the same except for their dc characteristics and available frequencies. valid combinations package type v=100-pin thin quad flat pack (tqfp) k=100-pin plastic quad flat pack (pqfp) v where: t c = case temperature am186eslvC25 valid combinations am188eslvC25 am188eslvC20 am186eslvC20 vc\w or kc\w am186esC25 am186esC33 am186esC40 am188esC25 am188esC33 am188esC40 vc\w or kc\w am188esC20 am186esC20 ki\w am186esC25 am188esC25 ki\w am188esC20 am186esC20 vc\w or kc\w vc\w or kc\w t a = ambient temperature c=eslv commercial (t a =0 c to +70 c) i=es industrial (t a =C40 c to +85 c) am186es high-performance, 80c186-compatible, 16-bit embedded microcontroller am188es high-performance, 80c188-compatible, 16-bit embedded microcontroller am186eslv high-performance, 80l186-compatible, low-voltage, 16-bit embedded microcontroller am188eslv high-performance, 80l188-compatible, low-voltage, 16-bit embedded microcontroller
am186/188es and am186/188eslv microcontrollers 5 preliminary table of contents distinctive characteristics ............................................................................................................ 1 general description ..................................................................................................................... 1 am186es microcontroller block diagram..................................................................................... 2 am188es microcontroller block diagram..................................................................................... 3 ordering information .................................................................................................................... 4 related amd products ................................................................................................................ 8 key features and benefits ........................................................................................................ 10 comparing the es to the 80c186 .............................................................................................. 11 comparing the es to the em ..................................................................................................... 11 tqfp connection diagrams and pinouts .................................................................................. 13 pqfp connection diagrams and pinouts ................................................................................. 19 logic symbolam186es microcontroller ................................................................................. 25 logic symbolam188es microcontroller ................................................................................. 26 pin descriptions ......................................................................................................................... 27 pins that are used by emulators .................................................................................. 27 pin terminology ............................................................................................................. 27 a19Ca0 .......................................................................................................................... 27 ad15Cad8 (am186es microcontroller) .......................................................................... 27 ao15Cao8 (am188es microcontroller) ........................................................................ 27 ad7Cad0 ....................................................................................................................... 27 ale ................................................................................................................................ 27 ardy ............................................................................................................................. 27 bhe /aden (am186es microcontroller only) ................................................................ 28 clkouta ...................................................................................................................... 28 clkoutb ...................................................................................................................... 28 cts 0/enrx 0/pio21 ...................................................................................................... 28 den /ds /pio5 ................................................................................................................ 29 drq0/int5/pio12 ......................................................................................................... 29 drq1/int6/pio13 ......................................................................................................... 29 dt/r /pio4 ..................................................................................................................... 29 gnd ............................................................................................................................... 29 hlda ............................................................................................................................. 29 hold ............................................................................................................................. 29 int0 ............................................................................................................................... 30 int1/select ................................................................................................................ 30 int2/inta 0/pwd/pio31 ............................................................................................... 30 int3/inta 1/irq ............................................................................................................. 30 int4/pio30 .................................................................................................................... 31 lcs /once 0 ................................................................................................................... 31 mcs 0 (mcs 0/pio14) .................................................................................................... 31 mcs 2Cmcs 1 (mcs 2/pio24, mcs 1/pio15) ................................................................. 31 mcs 3/rfsh /pio25 ....................................................................................................... 31 nmi ................................................................................................................................ 32 pcs 1Cpcs 0 (pcs 1/pio17, pcs 0/pio16) .................................................................... 32 pcs 2/cts 1/enrx 1/pio18 ........................................................................................... 32 pcs 3/rts 1/rtr 1/pio19 .............................................................................................. 32 pcs 5/a1/pio3 ............................................................................................................... 33 pcs 6/a2/pio2 ............................................................................................................... 33 pio31Cpio0 (shared) .................................................................................................... 33 rd .................................................................................................................................. 35 res ................................................................................................................................ 35 rfsh 2/aden (am188es microcontroller only) ............................................................ 35
6 am186/188es and am186/188eslv microcontrollers preliminary rts 0/rtr 0/pio20 ........................................................................................................ 35 rxd0/pio23 .................................................................................................................. 35 rxd1/pio28 .................................................................................................................. 35 s 2Cs 0 ............................................................................................................................ 35 s6/lock /clkdiv 2/pio29 ............................................................................................. 36 srdy/pio6 .................................................................................................................... 36 tmrin0/pio11 .............................................................................................................. 36 tmrin1/pio0 ................................................................................................................ 36 tmrout0/pio10 .......................................................................................................... 36 tmrout1/pio1 ............................................................................................................ 36 txd0/pio22 ................................................................................................................... 36 txd1/pio27 ................................................................................................................... 36 ucs /once 1 .................................................................................................................. 36 uzi /pio26 ...................................................................................................................... 37 v cc ................................................................................................................................ 37 whb (am186es microcontroller only) .......................................................................... 37 wlb (am186es microcontroller only) ........................................................................... 37 wb (am188es microcontroller only) ............................................................................. 37 wr ................................................................................................................................. 37 x1 ................................................................................................................................... 37 x2 ................................................................................................................................... 37 functional description ................................................................................................................ 38 bus operation ............................................................................................................................ 39 bus interface unit ...................................................................................................................... 41 peripheral control block (pcb) ................................................................................................. 42 clock and power management .................................................................................................. 44 chip-select unit ......................................................................................................................... 46 refresh control unit .................................................................................................................. 47 interrupt control unit ................................................................................................................. 48 timer control unit ...................................................................................................................... 48 direct memory access (dma) ................................................................................................... 49 pulse width demodulation ........................................................................................................ 51 asynchronous serial ports ........................................................................................................ 51 programmable i/o (pio) pins .................................................................................................... 52 absolute maximum ratings ....................................................................................................... 53 operating ranges ...................................................................................................................... 53 dc characteristics over commercial operating ranges .......................................................... 53 commercial switching characteristics and waveforms ............................................................ 61 tqfp physical dimensions ........................................................................................................ 98 pqfp physical dimensions ...................................................................................................... 100
am186/188es and am186/188eslv microcontrollers 7 preliminary list of figures figure 1 am186es microcontroller example system design .............................................. 10 figure 2 80c186 microcontroller example system design ................................................. 11 figure 3 two-component address ...................................................................................... 38 figure 4 am186es microcontroller address bus normal operation................................ 39 figure 5 am186es microcontrolleraddress bus disable in effect ................................... 40 figure 6 am188es microcontroller address bus normal operation ............................... 40 figure 7 am188es microcontroller address bus disable in effect................................... 41 figure 8 am186es and am188es microcontrollers oscillator configurations .................... 44 figure 9 clock organization ................................................................................................ 45 figure 10 dma unit block diagram ....................................................................................... 50 figure 11 typical i cc versus frequency for the am186eslv and am188eslv ................... 54 figure 12 typical i cc versus frequency for the am186es and am188es............................. 54 figure 13 thermal resistance( c/watt) ................................................................................ 55 figure 14 thermal characteristics equations ........................................................................ 55 figure 15 typical ambient temperatures for pqfp with a 2-layer board ............................ 57 figure 16 typical ambient temperatures for tqfp with a 2-layer board ............................ 58 figure 17 typical ambient temperatures for pqfp with a 4-layer to 6-layer board .......... 59 figure 18 typical ambient temperatures for tqfp with a 4-layer to 6-layer board ........... 60 list of tables table 1 data byte encoding ............................................................................................... 28 table 2 numeric pio pin designations .............................................................................. 34 table 3 alphabetic pio pin designations ........................................................................... 34 table 4 bus cycle encoding ............................................................................................... 35 table 5 segment register selection rules ........................................................................ 38 table 6 programming am186es microcontroller bus width .............................................. 42 table 7 peripheral control block register map .................................................................. 43 table 8 am186es microcontroller maximum dma transfer rates .................................... 49 table 9 typical power consumption for the am186eslv and am188eslv...................... 54 table 10 thermal characteristics ( c/watt) ......................................................................... 55 table 11 typical power consumption calculation ............................................................... 56 table 12 junction temperature calculation ......................................................................... 56 table 13 typical ambient temperatures for pqfp with a 2-layer board ............................ 57 table 14 typical ambient temperatures for tqfp with a 2-layer board ............................ 58 table 15 typical ambient temperatures for pqfp with a 4-layer to 6-layer board .......... 59 table 16 typical ambient temperatures for tqfp with a 4-layer to 6-layer board ........... 60
8 am186/188es and am186/188eslv microcontrollers preliminary related amd products e86 ? family devices device description 80c186 16-bit microcontroller 80c188 16-bit microcontroller with 8-bit external data bus 80l186 low-voltage, 16-bit microcontroller 80l188 low-voltage, 16-bit microcontroller with 8-bit external data bus am186em high-performance, 80c186-compatible, 16-bit embedded microcontroller am188em high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186emlv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188emlv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186es high-performance, 80c186-compatible, 16-bit embedded microcontroller am188es high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186eslv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188eslv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186er high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal ram am188er high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 kbyte of internal ram lan ? sc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at microcontroller lansc400 single-chip, low-power, pc/at-compatible microcontroller am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus at peripheral microcontrollers 186 peripheral microcontrollers lansc400 microcon t roller 80c186 and 80c188 microcontrollers microprocessors lansc300 microcon t roller am386sx/dx microprocessors am486dx microprocessor amd-k5 ? microprocessor time the e86 family of embedded microprocessors and microcontrollers am186es and am188es microcontrollers am186em and am188em microcontrollers am186 and am188 future lansc310 microcon t roller 80l186 and 80l188 microcontrollers am186emlv & am188emlv microcontrollers am186eslv & am188eslv microcontrollers 32-bit future am186er and am188er microcontrollers future k86 ? am486 future
am186/188es and am186/188eslv microcontrollers 9 preliminary related documents the following documents provide additional information regarding the am186es and am188es microcontrollers: n the am186es and am188es microcontrollers users manual, order# 21096 n the fusione86 sm catalog, order# 19255 third-party development support products the fusione86 sm program of partnerships for application solutions provides the customer with an array of products designed to meet critical time-to- market needs. products and solutions available from the amd fusione86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. of- fices, international offices, and a customer training cen- ter. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff who can answer e86 family hard- ware and software development questions. hotline and world wide web support for answers to technical questions, amd provides a toll-free number for direct access to our corporate ap- plications hotline. also available is the amd world wide web home page and ftp site, which provides the latest e86 family product information, including technical information and data on upcoming product re- leases. for technical support questions on all e86 products, send e-mail to lpd.support@amd.com. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline world wide web home page and ftp site to access the amd home page go to http:// www.amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com. documentation and literature free e86 family information such as data books, users manuals, data sheets, application notes, the fusione86 partner solutions catalog, and other litera- ture is available with a simple phone call. internation- ally, contact your local amd sales office for complete e86 family literature. literature ordering (800) 222-9323 toll-free for u.s. and canada (512) 602-5651 direct dial worldwide (800) 222-9323 amd facts-on-demand? fax information service, toll-free for u.s. and canada
10 am186/188es and am186/188eslv microcontrollers preliminary key features and benefits the am186es and am188es microcontrollers extend the amd family of microcontrollers based on the industry-standard x86 architecture. the am186es and am188es microcontrollers are higher-performance, more integrated versions of the 80c186/188 microprocessors, offering an attractive migration path. in addition, the am186es and am188es microcontrollers offer application-specific features that can enhance the system functionality of the am186em and am188em microcontrollers. upgrading to the am186es and am188es microcontrollers is an attractive solution for several reasons: n minimized total system cost new peripherals and on-chip system interface logic on the am186es and am188es microcontrollers reduce the cost of existing 80c186/188 designs. n x86 software compatibility 80c186/188-com- patible and upward-compatible with the other mem- bers of the amd e86 family. the x86 architecture is the most widely used and supported computer ar- chitecture in the world. n enhanced performance the am186es and am188es microcontrollers increase the perfor- mance of 80c186/188 systems, and the nonmulti- plexed address bus offers faster, unbuffered access to memory. n enhanced functionality the new and enhanced on-chip peripherals of the am186es and am188es microcontrollers include two asynchronous serial ports, 32 pios, a watchdog timer, additional inter- rupt pins, a pulse width demodulation option, dma directly to and from the serial ports, 8-bit and 16-bit static bus sizing, a psram controller, a 16-bit reset configuration register, and enhanced chip-select functionality. application considerations the integration enhancements of the am186es and am188es microcontrollers provide a high- performance, low-system-cost solution for 16-bit embedded microcontroller designs. the nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. clock generation the integrated clock generation circuitry of the am186es and am188es microcontrollers allows the use of a times-one crystal frequency. the design shown in figure 1 achieves 40-mhz cpu operation, while using a 40-mhz crystal. memory interface the integrated memory controller logic of the am186es and am188es microcontrollers provides a direct address bus interface to memory devices. it is not necessary to use an external address latch controlled by the address latch enable (ale) signal. individual byte-write-enable signals eliminate the need for external high/low byte-write-enable circuitry. the maximum bank size that is programmable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. the improved memory timing specifications for the am186es and am188es microcontrollers allow no- wait-state operation with 70-ns memory access times at a 40-mhz cpu clock speed. this reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. figure 1 also shows an implementation of an rs-232 console or modem communications port. the rs-232- to-cmos voltage-level converter is required for the electrical interface with the external device. figure 1. am186es microcontroller example system design direct memory interface example figure 1 illustrates the am186es microcontrollers direct memory interface. the processor a19Ca0 bus connects to the memory address inputs, the ad bus x2 x1 rs-232 level converter serial port 0 lcs ucs whb wlb we address data oe cs we rd we address data oe cs we ad15Cad0 a19Ca0 flash prom static ram am186es microcontroller 40-mhz crystal serial port 1 pw pwd input
am186/188es and am186/188eslv microcontrollers 11 preliminary connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. the rd output connects to the sram output enable (oe ) pin for read operations. write operations use the byte-write enables connected to the sram write enable (we ) pins. the example design uses 2-mbit memory technology (256 kbytes) to fully populate the available address space. two flash prom devices provide 512 kbytes of nonvolatile program storage, and two static ram devices provide 512 kbytes of data storage area. comparing the es to the 80c186 figure 1 shows an example system using a 40-mhz am186es microcontroller. figure 2 shows a comparable system implementation with an 80c186. because of its superior integration, the am186es microcontroller system does not require the support devices that are required on the 80c186 example system. in addition, the am186es microcontroller provides significantly better performance with its 40- mhz clock rate. figure 2. 80c186 microcontroller example system design comparing the es to the em table1 compared to the am186em and am188em microcontrollers, the am186es and am188es microcontrollers have the following additional features: n two full-featured asynchronous serial ports n the ability to use dma to and from the serial ports n two additional external interrupt signals n enhancements to the watchdog timer to improve its security and functionality n a pulse width demodulation option n a data strobe bus interface option for den n ardy functionality is changed to allow both edges of ardy to be asynchronous to the clock n an option to have all mcs space asserted through mcs 0 n on the am186es microcontroller, static bus sizing allows ucs space to use a 16-bit data bus, while lcs space can be either 8-bit or 16-bit. all non- ucs and non-lcs memory and i/o accesses can be 8-bit or 16-bit. this capability is available only on the am186es microcontroller; the am188es micro- controller has a uniform 8-bit access width. n the synchronous serial interface is removed n on the es, row addresses are not driven on dram refreshes two asynchronous serial ports the am186es and am188es microcontrollers have two identical asynchronous serial ports. each serial ucs wr we oe cs ad15Cad0 ale 40-mhz crystal address data timer 0C2 int3 dma 0C1 clkout 20 mhz x2 x1 sram we we address data oe cs rd lcs bhe a0 pal latch pcs 0 latch serial port rs-232 level converter int2Cint0 pios am29f200 flash
12 am186/188es and am186/188eslv microcontrollers preliminary port operates independently and has the following features: n full-duplex operation n 7-bit, 8-bit, or 9-bit operation n even, odd, or no parity n one stop bit n long or short break character recognition n parity error, framing error, overrun error, and break character detection n configurable hardware handshaking with cts , rts , enrx , and rtr n dma to and from the serial ports n separate maskable interrupts for each port n multiprocessor 9-bit protocol n independent baud rates for each port n maximum baud rate of 1/16th of the cpu clock rate n double-buffered transmit and receive n programmable interrupt generation for transmit, re- ceive, and/or error detection dma and the serial ports the am186es and am188es microcontrollers can dma directly to and from the serial ports. dma and serial port transfer is accomplished by programming the dma controller to perform transfers between a data source in memory or i/o space and a serial port transmit or receive register. the two dma channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. two additional external interrupts two new interrupts, int5 and int6, are multiplexed with the dma request signals, drq0 and drq1. if a dma channel is not enabled, or if it is not using external synchronization, then the associated pin can be used as an external interrupt. int5 and int6 can also be used in conjunction with the dma terminal count interrupts. enhanced watchdog timer the am186es and am188es microcontrollers provide a true watchdog timer that can be configured to generate either an nmi interrupt or a system reset upon timeout. the watchdog timer supports up to a 1.67-second timeout period in a 40-mhz system. after reset, the watchdog timer defaults to enabled and can be modified or disabled only one time. if the timer is not disabled, the application program must periodically reset the timer by writing a specific key sequence to the watchdog timer control register. if the timer is not reset before it counts down, either an nmi or a system reset is issued, depending on the configuration of the timer. pulse width demodulation option the am186es and am188es microcontrollers provide pulse width demodulation by adding a schmitt trigger buffer to the int2 pin. if pulse width demodulation mode is enabled, timer 0 and timer 1 are used to determine the pulse width of the signal period. separate maskable interrupts are generated on the rising and falling edge of the pulse input. in pulse width demodulation mode, the external pins int4, timerin0, and timerin1 are available as pios, but not as their normal functionality. data strobe bus interface option the am186es and am188es microcontrollers provide a truly asynchronous bus interface that allows the use of 68k-type peripherals. this implementation combines a new ds data strobe signal (multiplexed with den ) with a truly asynchronous ardy ready input. when ds is asserted, the data and address signals are valid. a chip-select signal, ardy, ds , and other control signals (rd /wr ) can control the interface of 68k-type external peripherals to the ad bus. mcs 0 asserted for all mcs option when the mcs 0-only mode is enabled in the am186es and am188es microcontrollers, the entire middle chip-select range is selected through mcs 0. the remaining mcs pins are available as pios or alternate functions. ardy functionality change in the am186es and am188es microcontrollers, the ardy signal is changed to allow both edges of ardy to be asynchronous to the clock. on the am186em and am188em microcontrollers, proper operation was not guaranteed if ardy did not meet the specification relative to the clock for all edges except the falling edge of a normally-ready system (relative to the rising edge of clkouta). to guarantee the number of wait states inserted, ardy or srdy must be synchronized to clkouta. if the falling edge of ardy is not synchronized to clkouta as specified, an additional clock period can be added. 8-bit and 16-bit bus sizing option the am186es microcontroller allows switchable 8-bit and 16-bit bus sizing based on chip selects for three chip-select regions. the am188es microcontroller supports only 8-bit data widths. on the am186es microcontroller, the upper chip select (ucs) region is always 16 bits, so memory used for boot code at power-on reset must be 16-bit memory. however, the lcs memory region, memory that is not ucs or lcs (including memory mapped to mcs and pcs ), and i/o space can be independently configured as 8-bit or 16-bit.
am186/188es and am186/188eslv microcontrollers 13 preliminary tqfp connection diagrams and pinouts am186es microcontroller top side view100-pin thin quad flat pack (tqfp) note: pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ad8 2 ad1 3 ad9 4 ad2 5 ad10 6 ad3 7 ad11 8 ad4 9 ad12 10 ad5 11 12 ad13 13 ad6 14 15 ad14 16 ad7 17 ad15 18 19 20 txd1 21 rxd1 22 23 rxd0 24 txd0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0/int5 99 drq1/int6 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1/pio0 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq rts0/rtr0 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2/pio24 3/ gnd gnd gnd gnd gnd whb wlb dt/r den /ds mcs 0 mcs 1 bhe/aden wr rd s2 s1 s0 inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s 6/lock /clkdiv 2 uzi cts 0/enrx 0 /pwd /rts1/rtr1 /cts1/enrx1 am186es microcontroller
14 am186/188es and am186/188eslv microcontrollers preliminary tqfp pin assignmentsam186es microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1ad0 26 rts 0/rtr 0/ pio20 51 a11 76 int3/inta 1/irq 2 ad8 27 bhe /aden 52 a10 77 int2/inta 0/pwd/ pio31 3ad1 28wr 53 a9 78 int1/select 4 ad9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs /once 1 6 ad10 31 ardy 56 a6 81 lcs /once 0 7ad3 32s 2 57a5 82pcs 6/a2/pio2 8ad11 33s 1 58a4 83pcs 5/a1/pio3 9ad4 34s 0 59a3 84v cc 10 ad12 35 gnd 60 a2 85 pcs 3/rts 1/ rtr 1/ pio19 11ad5 36x1 61v cc 86 pcs 2/cts 1/ enrx 1/pio18 12gnd 37x2 62a1 87gnd 13 ad13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 whb 90 v cc 16 ad14 41 gnd 66 wlb 91 mcs 2/pio24 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh / pio25 18 ad15 43 a18/pio8 68 hold 93 gnd 19 s6/lock /clkdiv 2/ pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd1/pio27 46 a16 71 dt/r/ pio4 96 tmrout1/pio1 22 rxd1/pio28 47 a15 72 den /ds /pio5 97 tmrout0/pio10 23 cts 0/enrx 0/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 rxd0/pio23 49 a13 74 mcs 1/pio15 99 drq1/int6/pio13 25 txd0/pio22 50 a12 75 int4/pio30 100 drq0/int5/pio12
am186/188es and am186/188eslv microcontrollers 15 preliminary tqfp pin designationsam186es microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 87 rxd1 22 a1 62 ad6 14 gnd 93 s 034 a2 60 ad7 17 hlda 67 s 133 a3 59 ad8 2 hold 68 s 232 a4 58 ad9 4 int0 79 s6/lock / clkdiv 2/pio29 19 a5 57 ad10 6 int1/select 78 srdy/pio6 69 a6 56 ad11 8 int2/inta 0/ pwd/pio31 77 tmrin0/pio11 98 a7 55 ad12 10 int3/inta 1/irq 76 tmrin1/pio0 95 a8 54 ad13 13 int4/pio30 75 tmrout0/ pio10 97 a9 53 ad14 16 lcs /once 0 81 tmrout1/pio1 96 a10 52 ad15 18 mcs 0/pio14 73 txd0/pio22 25 a11 51 ale 30 mcs 1/pio15 74 txd1 21 a12 50 ardy 31 mcs 2/pio24 91 ucs /once 180 a13 49 bhe /aden 27 mcs 3/rfsh /pio25 92 uzi /pio26 20 a14 48 clkouta 39 nmi 70 v cc 15 a15 47 clkoutb 40 pcs 0/pio16 89 v cc 38 a16 46 cts 0/enrx 0/ pio21 23 pcs 1/pio17 88 v cc 44 a17/pio7 45 den /ds /pio5 72 pcs 2/cts 1/ enrx 1/pio18 86 v cc 61 a18/pio8 43 drq0/int5/pio12 100 pcs 3/rts 1/rtr 1/ pio19 85 v cc 84 a19/pio9 42 drq1/int6/pio13 99 pcs 5/a1/pio3 83 v cc 90 ad0 1 dt/r /pio4 71 pcs 6/a2/pio2 82 whb 65 ad1 3 gnd 12 rd 29 wlb 66 ad2 5 gnd 35 res 94 wr 28 ad3 7 gnd 41 rts 0/rtr 0/pio20 26 x1 36 ad4 9 gnd 64 rxd0/pio23 24 x2 37
16 am186/188es and am186/188eslv microcontrollers preliminary connection diagram am188es microcontroller top side view100-pin thin quad flat pack (tqfp) note: pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ao8 2 ad1 3 ao9 4 ad2 5 ao10 6 ad3 7 ao11 8 ad4 9 ao12 10 ad5 11 12 ao13 13 ad6 14 15 ao14 16 ad7 17 ao15 18 19 20 txd1 21 rxd1 22 23 rxd0 24 txd0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0/int5 99 drq1/int6 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq rts0/rtr0 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2 3/ gnd gnd gnd gnd gnd gnd wb dt/r den /ds mcs 0 mcs 1 rfsh2/aden wr rd s2 s1 s0 inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s6/lock /clkdiv 2 uzi cts 0/enrx 0 /pwd /rts1/rtr1 /cts1/enrx1 am188es microcontroller
am186/188es and am186/188eslv microcontrollers 17 preliminary tqfp pin designationsam188es microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1ad0 26 rts 0/rtr 0/ pio20 51 a11 76 int3/inta 1/irq 2ao8 27rfsh 2/aden 52 a10 77 int2/inta 0/ pwd/pio31 3ad1 28wr 53 a9 78 int1/select 4ao9 29rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs /once 1 6ao10 31ardy 56a6 81lcs /once 0 7ad3 32s 257a5 82pcs 6/a2/pio2 8ao11 33s 158a4 83pcs 5/a1/pio3 9ad4 34s 059a3 84v cc 10 ao12 35 gnd 60 a2 85 pcs 3/rts 1/rtr 1/ pio19 11 ad5 36 x1 61 v cc 86 pcs 2/cts 1/enrx 1/ pio18 12 gnd 37 x2 62 a1 87 gnd 13 ao13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 gnd 90 v cc 16 ao14 41 gnd 66 wb 91 mcs 2/pio24 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh /pio25 18 ao15 43 a18/pio8 68 hold 93 gnd 19 s6/lock / clkdiv 2/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd1/pio27 46 a16 71 dt/r/ pio4 96 tmrout1/pio1 22 rxd1/pio28 47 a15 72 den /ds /pio5 97 tmrout0/pio10 23 cts 0/enrx 0/ pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 rxd0/pio23 49 a13 74 mcs 1/pio15 99 drq1/int6/pio13 25 txd0/pio22 50 a12 75 int4/pio30 100 drq0/int5/pio12
18 am186/188es and am186/188eslv microcontrollers preliminary tqfp pin designationsam188es microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 87 rxd0/pio23 24 a1 62 ad6 14 gnd 93 rxd1/pio28 22 a2 60 ad7 17 hlda 67 s 034 a3 59 ale 30 hold 68 s 133 a4 58 ao8 2 int0 79 s 232 a5 57 ao9 4 int1/select 78 s6/lock / clkdiv 2/pio29 19 a6 56 ao10 6 int2/inta 0/ pwd/pio31 77 srdy/pio6 69 a7 55 ao11 8 int3/inta 1/irq 76 tmrin0/pio11 98 a8 54 ao12 10 int4/pio30 75 tmrin1/pio0 95 a9 53 ao13 13 lcs /once 0 81 tmrout0/pio10 97 a10 52ao14 16mcs 0/pio14 73 tmrout1/pio1 96 a11 51ao15 18mcs 1/pio15 74 txd0/pio22 25 a12 50 ardy 31 mcs 2/pio24 91 txd1/pio27 21 a13 49 clkouta 39 mcs 3/rfsh / pio25 92 ucs /once 180 a14 48 clkoutb 40 nmi 70 uzi /pio26 20 a15 47 cts 0/enrx 0/ pio21 23 pcs 0/pio16 89 v cc 15 a16 46 den /ds /pio5 72 pcs 1/pio17 88 v cc 38 a17/pio7 45 drq0/int5/ pio12 100 pcs 2/cts 1/ enrx 1/pio18 86 v cc 44 a18/pio8 43 drq1/int6/ pio13 99 pcs 3/rts 1/ rtr 1/ pio19 85 v cc 61 a19/pio9 42 dt/r /pio4 71 pcs 5/a1/pio3 83 v cc 84 ad0 1 gnd 12 pcs 6/a2/pio2 82 v cc 90 ad1 3 gnd 35 rd 29 wb 66 ad2 5 gnd 41 res 94 wr 28 ad3 7 gnd 64 rfsh 2/aden 27 x1 36 ad4 9 gnd 65 rts 0/rtr 0/ pio20 26 x2 37
am186/188es and am186/188eslv microcontrollers 19 preliminary pqfp connection diagrams and pinouts am186es microcontroller top side view100-pin plastic quad flat pack (pqfp) note: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd1 rxd1 cts0/enrx0 rxd0 txd0 gnd gnd ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/lock/clkdiv2 v cc v cc am186es microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bhe /aden uzi whb wlb den/ds mcs0 wr rd s 2 s 1 s 0 mcs 1 int3/inta 1/irq int2/inta 0/pwd int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3/rts 1/rtr 1 pcs 2/cts 1/enrx 1 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res rts 0/rtr 0 drq 1/int6 drq 0/int5
20 am186/188es and am186/188eslv microcontrollers preliminary pqfp pin designationsam186es microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 rxd0/pio23 26 a13 51 mcs 1/pio15 76 drq1/int6/pio13 2 txd0/pio22 27 a12 52 int4/pio30 77 drq0/int5/pio12 3 rts 0/rtr 0/ pio20 28 a11 53 int3/inta 1/irq 78 ad0 4bhe /aden 29 a10 54 int2/inta 0/ pwd/pio31 79 ad8 5wr 30 a9 55 int1/select 80 ad1 6rd 31 a8 56 int0 81 ad9 7 ale 32 a7 57 ucs /once 182ad2 8 ardy 33a6 58lcs /once 083ad10 9s 2 34a5 59pcs 6/a2/pio2 84 ad3 10 s 1 35a4 60pcs 5/a1/pio3 85 ad11 11 s 0 36a3 61v cc 86 ad4 12 gnd 37 a2 62 pcs 3/rts 1/rtr 1/ pio19 87 ad12 13 x1 38 v cc 63 pcs 2/cts 1/ enrx 1/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ad13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 whb 67 v cc 92 v cc 18 gnd 43 wlb 68 mcs 2/pio24 93 ad14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ad15 21 v cc 46 srdy/pio6 71 res 96 s6/lock / clkdiv 2/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /pio26 23 a16 48 dt/r/ pio4 73 tmrout1/pio1 98 txd1/pio27 24 a15 49 den /ds /pio5 74 tmrout0/pio10 99 rxd1/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 cts 0/enrx 0/pio21
am186/188es and am186/188eslv microcontrollers 21 preliminary pqfp pin designationsam186es microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 70 rxd1/pio28 99 a1 39 ad6 91 gnd 89 s 011 a2 37 ad7 94 hlda 44 s 110 a3 36 ad8 79 hold 45 s 29 a4 35 ad9 81 int0 56 s6/lock / clkdiv 2/pio29 96 a5 34 ad10 83 int1/select 55 srdy/pio6 46 a6 33 ad11 85 int2/inta 0/ pwd/pio31 54 tmrin0/pio11 75 a7 32 ad12 87 int3/inta 1/irq 53 tmrin1/pio0 72 a8 31 ad13 90 int4/pio30 52 tmrout0/ pio10 74 a9 30 ad14 93 lcs /once 0 58 tmrout1/pio1 73 a10 29 ad15 95 mcs 0/pio14 50 txd0/pio22 2 a11 28 ale 7 mcs 1/pio15 51 txd1/pio27 98 a12 27 ardy 8 mcs 2/pio24 68 ucs /once 157 a13 26 bhe /aden 4mcs 3/rfsh /pio25 69 uzi /pio26 97 a14 25 clkouta 16 nmi 47 v cc 15 a15 24 clkoutb 17 pcs 0/pio16 66 v cc 21 a16 23 cts 0/enrx 0/ pio21 100 pcs 1/pio17 65 v cc 38 a17/pio7 22 den /ds /pio5 49 pcs 2/cts 1/enrx 1/ pio18 63 v cc 61 a18/pio8 20 drq0/int5/pio12 77 pcs 3/rts 1/rtr 1/ pio19 62 v cc 67 a19/pio9 19 drq1/int6/pio13 76 pcs 5/a1/pio3 60 v cc 92 ad0 78 dt/r /pio4 48 pcs 6/a2/pio2 59 whb 42 ad1 80 gnd 12 rd 6wlb 43 ad2 82 gnd 18 res 71 wr 5 ad3 84 gnd 41 rts 0/rtr 0/pio20 3 x1 13 ad4 86 gnd 64 rxd0/pio23 1 x2 14
22 am186/188es and am186/188eslv microcontrollers preliminary connection diagram am188es microcontroller top side view100-pin plastic quad flat pack (pqfp) note: pin 1 is marked for orientation. ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 ao13 ad6 ao14 ad7 ao15 txd1 rxd1 cts0/enrx0 rxd0 txd0 gnd gnd ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/lock/clkdiv2 drq1/int6 drq0/int5 v cc v cc am188es microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 r fsh 2/aden uzi gnd wb den/ds mcs0 wr rd s 2 s 1 s 0 mcs 1 int3/inta 1/irq int2/inta 0/pwd int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3/rts 1/rtr 1 pcs 2/cts 1/enrx 1 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res rts 0/rtr 0
am186/188es and am186/188eslv microcontrollers 23 preliminary pqfp pin designationsam188es microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 rxd0/pio23 26 a13 51 mcs 1/pio15 76 drq1/int6/pio13 2 txd0/pio22 27 a12 52 int4/pio30 77 drq0/int5/pio12 3 rts 0/rtr 0/ pio20 28 a11 53 int3/inta 1/irq 78 ad0 4rfsh 2/aden 29 a10 54 int2/inta 0/ pwd/pio31 79 ao8 5wr 30 a9 55 int1/select 80 ad1 6rd 31 a8 56 int0 81 ao9 7 ale 32 a7 57 ucs /once 182ad2 8 ardy 33a6 58lcs /once 083ao10 9s 2 34a5 59pcs 6/a2/pio2 84 ad3 10 s 1 35a4 60pcs 5/a1/pio3 85 ao11 11 s 0 36a3 61v cc 86 ad4 12 gnd 37 a2 62 pcs 3/rts 1/rtr 1/ pio19 87 ao12 13 x1 38 v cc 63 pcs 2/cts 1/enrx 1/ pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ao13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 gnd 67 v cc 92 v cc 18 gnd 43 wb 68 mcs 2/pio24 93 ao14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ao15 21 v cc 46 srdy/pio6 71 res 96 s6/lock / clkdiv 2/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /pio26 23 a16 48 dt/r/ pio4 73 tmrout1/pio1 98 txd1/pio27 24 a15 49 den /ds /pio5 74 tmrout0/pio10 99 rxd1/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 cts 0/enrx 0/pio21
24 am186/188es and am186/188eslv microcontrollers preliminary pqfp pin designationsam188es microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 70 rxd0/pio23 1 a1 39 ad6 91 gnd 89 rxd1/pio28 99 a2 37 ad7 94 hlda 44 s 011 a3 36 ale 7 hold 45 s 110 a4 35 ao8 79 int0 56 s 29 a5 34 ao9 81 int1/select 55 s6/lock / clkdiv 2/pio29 96 a6 33 ao10 83 int2/inta 0/ pwd/pio31 54 srdy/pio6 46 a7 32 ao11 85 int3/inta 1/irq 53 tmrin0/pio11 75 a8 31 ao12 87 int4/pio30 52 tmrin1/pio0 72 a9 30 ao13 90 lcs /once 058 tmrout0/ pio10 74 a10 29 ao14 93 mcs 0/pio14 50 tmrout1/pio1 73 a11 28 ao15 95 mcs 1/pio15 51 txd0/pio22 2 a12 27 ardy 8 mcs 2/pio24 68 txd1/pio27 98 a13 26 clkouta 16 mcs 3/rfsh /pio25 69 ucs /once 157 a14 25clkoutb 17nmi 47uzi /pio26 97 a15 24 cts 0/enrx 0/ pio21 100 pcs 0/pio16 66 v cc 15 a16 23 den /ds /pio5 49 pcs 1/pio17 65 v cc 21 a17/pio7 22 drq0/int5/pio12 77 pcs 2/cts 1/enrx 1/ pio18 63 v cc 38 a18/pio8 20 drq1/int6/pio13 76 pcs 3/rts 1/rtr 1/ pio19 62 v cc 61 a19/pio9 19 dt/r /pio4 48 pcs 5/a1/pio3 60 v cc 67 ad0 78 gnd 12 pcs 6/a2/pio2 59 v cc 92 ad1 80 gnd 18 rd 6wb 43 ad2 82 gnd 41 res 71 wr 5 ad3 84 gnd 42 rfsh 2/aden 4x1 13 ad4 86 gnd 64 rts 0/rtr 0/pio20 3 x2 14
am186/188es and am186/188eslv microcontrollers 25 preliminary logic symbolam186es microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see pin descriptions beginning on page 27 and table 2 on page 34 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb a19Ca0 ad15Cad0 ale whb wlb rd wr s 2Cs 0 hold hlda dt/r den /ds ardy srdy tmrin0 tmrout0 20 16 clocks address and address/data buses bus control timer control res int4 int3/inta 1/irq int2/inta 0/pwd int1/select int0 nmi pcs 6/a2 pcs 5/a1 pcs 1Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq0/int5 pio32Cpio0 2 32 shared reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 3 tmrin1 tmrout1 3 mcs 3/rfsh s6/lock /clkdiv 2 bhe /aden uzi ** * * * * * * * * * * * * * * * * * * drq1/int6 drq0/int5 drq1/int6 * txd0 rxd0 * * cts 0/enrx 0 rts 0/rtr 0 * * txd1 rxd1 * * pcs 2/cts 1/enrx 1 pcs 3/rts 1/rtr 1 pcs 3/rts 1/rtr 1 * pcs 2/cts 1/enrx 1 * * *
26 am186/188es and am186/188eslv microcontrollers preliminary logic symbolam188es microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see pin descriptions beginning on page 27 and table 2 on page 34 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb a19Ca0 ad7Cad0 ale wb rd wr s 2Cs 0 hold hlda dt/r den /ds ardy srdy tmrin0 tmrout0 20 8 clocks address and address/data buses bus control timer control res int4 int3/inta 1/irq int2/inta 0/pwd int1/select int0 nmi pcs 6/a2 pcs 5/a1 pcs 1Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq0/int5 pio32Cpio0 2 32 shared reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 3 tmrin1 tmrout1 3 mcs 3/rfsh s6/lock /clkdiv 2 rfsh 2/aden uzi ** * * * * * * * * * * * * * * * * * * drq1/int6 drq0/int5 drq1/int6 * txd0 rxd0 * * cts 0/enrx 0 rts 0/rtr 0 * * txd1 rxd1 * * pcs 2/cts 1/enrx 1 pcs 3/rts 1/rtr 1 pcs 3/rts 1/rtr 1 * pcs 2/cts 1/enrx 1 * ao15Cao8 8 * *
am186/188es and am186/188eslv microcontrollers 27 preliminary pin descriptions pins that are used by emulators the following pins are used by emulators: a19Ca0, ao15Cao8, ad7Cad0, ale, bhe /aden (on the 186), clkouta, rfsh 2/aden (on the 188), rd , s 2Cs 0, s6/lock /clkdiv 2, and uzi . emulators require s6/lock /clkdiv 2 and uzi to be configured in their normal functionality as s6 and uzi , not as pios. if bhe /aden (on the 186) or rfsh 2/ aden (on the 188) is held low during the rising edge of res , s6 and uzi are configured in their normal functionality. pin terminology the following terms are used to describe the pins: input an input-only pin. output an output-only pin. input/output a pin that can be either input or output. synchronous synchronous inputs must meet setup and hold times in relation to clkouta. synchronous outputs are synchronous to clkouta. asynchronous inputs or outputs that are asynchronous to clkouta. a19Ca0 (a19/pio9, a18/pio8, a17/pio7) address bus (output, three-state, synchronous) these pins supply nonmultiplexed memory or i/o addresses to the system one half of a clkouta period earlier than the multiplexed address and data bus (ad15Cad0 on the 186 or ao15Cao8 and ad7C ad0 on the 188). during a bus hold or reset condition, the address bus is in a high-impedance state. ad15Cad8 (am186es microcontroller) ao15Cao8 (am188es microcontroller) address and data bus (input/output, three-state, synchronous, level-sensitive) address-only bus (output, three-state, synchronous, level-sensitive) ad15Cad8 on the am186es microcontroller, these time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an address to the system during the first period of a bus cycle (t 1 ). it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when whb is deasserted, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the 186, ao15Cao8 and ad7C ad0 for the 188) can also be used to load system configuration information into the internal reset configuration register. ao15Cao8 when the address bus is enabled on the am188es microcontroller, via the ad bit in the umcs and lmcs registers, the address-only bus (ao15C ao8) contains valid high-order address bits from bus cycles t 1 Ct 4 . these outputs are floated during a bus hold or reset. on the am188es microcontroller, ao15Cao8 combine with ad7Cad0 to form a complete multiplexed address bus while ad7Cad0 is the 8-bit data bus. ad7Cad0 address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. this bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t 1 ), and it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). in 8-bit mode on the am188es microcontroller, ad7Cad0 supplies the data. the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when wlb is deasserted, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the 186, ao15Cao8 and ad7C ad0 for the 188) can also be used to load system configuration information into the internal reset configuration register. ale address latch enable (output, synchronous) this pin indicates to the system that an address ap- pears on the address and data bus (ad15Cad0 for the 186 or ao15Cao8 and ad7Cad0 for the 188). the ad- dress is guaranteed to be valid on the trailing edge of ale. this pin is three-stated during once mode. this pin is not three-stated during a bus hold or reset. ardy asynchronous ready (input, asynchronous, level-sensitive) this pin is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the ardy
28 am186/188es and am186/188eslv microcontrollers preliminary pin is asynchronous to clkouta and is active high. to guarantee the number of wait states inserted, ardy or srdy must be synchronized to clkouta. if the falling edge of ardy is not synchronized to clkouta as specified, an additional clock period can be added. to always assert the ready condition to the microcontroller, tie ardy high. if the system does not use ardy, tie the pin low to yield control to srdy. bhe /aden (am186es microcontroller only) bus high enable (three-state, output, synchronous) address enable (input, internal pullup) bhe during a memory access, this pin and the least- significant address bit (ad0 or a0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe /aden and ad0 pins are encoded as shown in table 1. table 1. data byte encoding bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not need to be latched. bhe floats during bus hold and reset. on the am186es microcontroller, wlb and whb implement the functionality of bhe and ad0 for high and low byte-write enables. bhe /aden also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a refresh cycle is indicated when both bhe /aden and ad0 are high. during refresh cycles, the a bus and the ad bus are not guaranteed to provide the same address during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. psram refreshes also provide an additional rfsh signal (see the mcs 3/rfsh pin description on page 31). aden if bhe /aden is held high or left floating during power-on reset, the address portion of the ad bus (ad15Cad0 for the 186 or ao15Cao8 and ad7C ad0 for the 188) is enabled or disabled during lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. in this case, the memory address is accessed on the a19Ca0 pins. there is a weak internal pullup resistor on bhe /aden so no external pullup is required. this mode of operation reduces power consumption. if bhe /aden is held low on power-on reset, the ad bus drives both addresses and data, regardless of the da bit setting. the pin is sampled on the rising edge of res . (s6 and uzi also assume their normal functionality in this instance. see table 2 on page 34.) note: on the am188es microcontroller, ao15Cao8 are driven during the t 2C t 4 bus cycle, regardless of the setting of the da bit in the umcs and lmcs registers. clkouta clock output a (output, synchronous) this pin supplies the internal clock to the system. depending on the value of the system configuration register (syscon), clkouta operates at either the pll frequency, the power-save frequency, or is three- stated. clkouta remains active during reset and bus hold conditions. all ac timing specs that use a clock relate to clkouta. clkoutb clock output b (output, synchronous) this pin supplies an additional clock with a delayed output compared to clkouta. depending upon the value of the system configuration register (syscon), clkoutb operates at either the pll frequency, the power-save frequency, or is three-stated. clkoutb remains active during reset and bus hold conditions. clkoutb is not used for ac timing specs. cts 0/enrx 0/pio21 clear-to-send 0 (input, asynchronous) enable-receiver-request 0 (input, asynchronous) cts 0 this pin provides the clear to send signal for asynchronous serial port 0 when the enrx 0 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the cts 0 signal gates the transmission of data from the associated serial port transmit register. when cts 0 is asserted, the transmitter begins transmission of a frame of data, if any is available. if cts 0 is deasserted, the transmitter holds the data in the serial port transmit register. the value of cts 0 is checked only at the beginning of the transmission of the frame. enrx 0 this pin provides the enable receiver request for asynchronous serial port 0 when the enrx0 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the enrx 0 signal enables the receiver for the associated serial port. bhe ad0 type of bus cycle 0 0 word transfer 01 high byte transfer (bits 15C8) 1 0 low byte transfer (bits 7C0) 11refresh
am186/188es and am186/188eslv microcontrollers 29 preliminary den /ds /pio5 data enable (output, three-state, synchronous) data strobe (output, three-state, synchronous) den this pin supplies an output enable to an external data-bus transceiver. den is asserted during memory, i/o, and interrupt acknowledge cycles. den is deasserted when dt/r changes state. den floats during a bus hold or reset condition. ds the data strobe provides a signal where the write cycle timing is identical to the read cycle timing. when used with other control signals, ds provides an interface for 68k-type peripherals without the need for additional system interface logic. when ds is asserted, addresses are valid. when ds is asserted on writes, data is valid. when ds is asserted on reads, data can be asserted on the ad bus. note: this pin resets to den . drq0/int5/pio12 dma request 0 (input, synchronous, level-sensitive) maskable interrupt request 5 (input, asynchronous, edge-triggered) drq0 this pin indicates to the microcontroller that an external device is ready for dma channel 0 to perform a transfer. drq0 is level-triggered and internally synchronized. drq0 is not latched and must remain active until serviced. int5 if dma 0 is not enabled or dma 0 is not being used with external synchronization, int5 can be used as an additional external interrupt request. int5 shares the dma 0 interrupt type (0ah) and register control bits. int5 is edge-triggered only and must be held until the interrupt is acknowledged. drq1/int6/pio13 dma request 1 (input, synchronous, level-sensitive) maskable interrupt request 6 (input, asynchronous, edge-triggered) drq1 this pin indicates to the microcontroller that an external device is ready for dma channel 1 to perform a transfer. drq1 is level-triggered and internally synchronized. drq1 is not latched and must remain active until serviced. int6 if dma 1 is not enabled or dma 1 is not being used with external synchronization, int6 can be used as an additional external interrupt request. int6 shares the dma 1 interrupt type (0bh) and register control bits. int6 is edge-triggered only and must be held until the interrupt is acknowledged. dt/r /pio4 data transmit or receive (output, three-state, synchronous) this pin indicates in which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r floats during a bus hold or reset condition. gnd ground ground pins connect the microcontroller to the system ground. hlda bus hold acknowledge (output, synchronous) this pin is asserted high to indicate to an external bus master that the microcontroller has released control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress. it then relinquishes control of the bus to the external bus master by asserting hlda and floating den , rd , wr , s 2Cs 0, ad15Cad0, s6, a19Ca0, bhe , whb , wlb , and dt/r , and then driving the chip selects ucs , lcs , mcs 3Cmcs 0, pcs 6Cpcs 5, and pcs 3Cpcs 0 high. when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (for example, to refresh), it will deassert hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the microcontroller access to the bus. see the timing diagrams for bus hold on page 97. hold bus hold request (input, synchronous, level-sensitive) this pin indicates to the microcontroller that an external bus master needs control of the local bus. the am186es and am188es microcontrollers hold latency time is a function of the activity occurring in the processor when the hold request is received. a dram request will delay a hold request when both requests are made at the same time. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. for more information, see the hlda pin description on page 29.
30 am186/188es and am186/188eslv microcontrollers preliminary int0 maskable interrupt request 0 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int0 pin is not masked, the microcontroller transfers program execution to the location specified by the int0 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int0 until the request is acknowledged. int1/select maskable interrupt request 1 (input, asynchronous) slave select (input, asynchronous) int1 this pin indicates to the microcontroller that an interrupt request has occurred. if int1 is not masked, the microcontroller transfers program execution to the location specified by the int1 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int1 until the request is acknowledged. select when the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. the int0 pin must indicate to the microcontroller that an interrupt has occurred before the select pin indicates to the microcontroller that the interrupt type appears on the bus. int2/inta 0/pwd/pio31 maskable interrupt request 2 (input, asynchronous) interrupt acknowledge 0 (output, synchronous) pulse width demodulator (input, schmitt trigger) int2 this pin indicates to the microcontroller that an interrupt request has occurred. if the int2 pin is not masked, the microcontroller transfers program execution to the location specified by the int2 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int2 until the request is acknowledged. int2 becomes inta 0 when int0 is configured in cascade mode. inta 0 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int0. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. pwd if pulse width demodulation is enabled, pwd processes a signal through the schmitt trigger. pwd is used internally to drive timerin0 and int2, and pwd is inverted internally to drive timerin1 and int4. if int2 and int4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating pwd signal can be calculated by comparing the values in timer 0 and timer 1. in pwd mode, the signals timerin0/pio11, timerin1/pio0, and int4/pio30 can be used as pios. if they are not used as pios they are ignored internally. the level of int2/inta 0/pwd/pio31 is reflected in the pio data register for pio 31 as if it was a pio. int3/inta 1/irq maskable interrupt request 3 (input, asynchronous) interrupt acknowledge 1 (output, synchronous) slave interrupt request (output, synchronous) int3 this pin indicates to the microcontroller that an interrupt request has occurred. if the int3 pin is not masked, the microcontroller then transfers program execution to the location specified by the int3 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int3 until the request is acknowledged. int3 becomes inta 1 when int1 is configured in cascade mode. inta 1 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int1. the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. irq when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
am186/188es and am186/188eslv microcontrollers 31 preliminary int4/pio30 maskable interrupt request 4 (input, asynchronous) this pin indicates to the microcontroller that an interrupt request has occurred. if the int4 pin is not masked, the microcontroller then transfers program execution to the location specified by the int4 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee interrupt recognition, the requesting device must continue asserting int4 until the request is acknowledged. when pulse width demodulation mode is enabled, the int4 signal is used internally to indicate a high-to-low transition on the pwd signal. when pulse width demodulation mode is enabled, int4/pio30 can be used as a pio. lcs /once 0 lower memory chip select (output, synchronous, internal pullup) once mode request 0 (input) lcs this pin indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbytes. on the am186es microcontroller, lcs is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. lcs is held high during a bus hold condition. once 0 during reset, this pin and once 1 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 0 has a weak internal pullup resistor that is active only during reset. this pin is not three-stated during a bus hold condition. mcs 0 (mcs 0/pio14) midrange memory chip select 0 (output, synchronous, internal pullup) this pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. on the am186es microcontroller, mcs 0 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. mcs 0 is held high during a bus hold condition. in addition, it has weak internal pullup resistors that are active during reset. this signal functions like the corresponding signal in the am186em and am188em microcontrollers except that mcs 0 can be programmed as the chip select for the entire middle chip select address range. mcs 2Cmcs 1 (mcs 2/pio24, mcs 1/pio15) midrange memory chip selects (output, synchronous, internal pullup) these pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. on the am186es microcontroller, mcs 2Cmcs 1 are configured for 8-bit or 16-bit bus size by the auxiliary configuration register. mcs 2Cmcs 1 are held high during a bus hold condition. in addition, they have weak internal pullup resistors that are active during reset. these signals function like the signals in the am186em and am188em microcontrollers except that if mcs 0 is programmed to be active for the entire middle chip- select range, then these signals are available as pios. if they are not programmed as pios and if mcs 0 is programmed for the whole middle chip-select range, then these signals operate normally. mcs 3/rfsh /pio25 midrange memory chip select 3 (output, synchronous, internal pullup) automatic refresh (output, synchronous) mcs 3 this pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. the base address and size of the midrange memory block are programmable. on the am186es microcontroller, mcs 3 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. mcs 3 is held high during a bus hold condition. in addition, this pin has a weak internal pullup resistor that is active during reset. this signal functions like the corresponding signal in the am186em and am188em microcontrollers except that if mcs 0 is programmed for the entire middle chip- select range, then this signal is available as a pio. if mcs 3 is not programmed as a pio and if mcs 0 is programmed for the entire middle chip-select range, then this signal operates normally. depending on the chip configuration, this signal can serve as a memory rfsh . rfsh this pin provides a signal timed for auto refresh to psram or dram devices. it is only enabled to function as a refresh pulse when the psram or dram mode bit is set. an active low pulse is
32 am186/188es and am186/188eslv microcontrollers preliminary generated for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is met. this signal functions like the rfsh signal in the am186em and am188em microcontrollers except that the dram row address is not driven on dram refreshes. this pin is not three-stated during a bus hold condition. nmi nonmaskable interrupt (input, synchronous, edge-sensitive) this pin indicates to the microcontroller that an interrupt request has occurred. the nmi signal is the highest priority hardware interrupt and, unlike the int6Cint0 pins, cannot be masked. the microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when nmi is asserted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request registers. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the if (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable interrupts are re-enabled by software in the nmi interrupt service routine, via the sti instruction for example, the fact that an nmi is currently in service does not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt service routine for nmi should not enable the maskable interrupts. an nmi transition from low to high is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the interrupt is recognized, the nmi pin must be asserted for at least one clkouta period. pcs 1Cpcs 0 (pcs 1/pio17, pcs 0/pio16) peripheral chip selects (output, synchronous) these pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 3Cpcs 0 are held high during a bus hold condition. they are also held high during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 2/cts 1/enrx 1/pio18 peripheral chip select 2 (output, synchronous) clear-to-send 1 (input, asynchronous) enable-receiver-request 1 (input, asynchronous) pcs 2 this pin provides the peripheral chip select 2 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. the pcs 2 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 2 is held high during a bus hold or reset condition. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. cts 1 this pin provides the clear to send signal for asynchronous serial port 1 when the enrx1 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the cts 1 signal gates the transmission of data from the associated serial port transmit register. when cts 1 is asserted, the transmitter begins transmission of a frame of data, if any is available. if cts 1 is deasserted, the transmitter holds the data in the serial port transmit register. the value of cts 1 is checked only at the beginning of the transmission of the frame. enrx 1 this pin provides the enable receiver request for asynchronous serial port 1 when the enrx1 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the enrx 1 signal enables the receiver for the associated serial port. pcs 3/rts 1/rtr 1/pio19 peripheral chip select 3 (output, synchronous) ready-to-send 1 (output, asynchronous) ready-to-receive 1 (output, asynchronous) pcs 3 this pin provides the peripheral chip select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. the pcs 3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 3 is held high during a bus hold or reset condition.
am186/188es and am186/188eslv microcontrollers 33 preliminary unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. rts 1 this pin provides the ready to send signal for asynchronous serial port 1 when the rts 1 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the rts 1 signal is asserted when the associated serial port transmit register contains data which has not been transmitted. rtr 1 this pin provides the ready to receive signal for asynchronous serial port 1 when the rts 1 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 1 control register is set). the rtr 1 signal is asserted when the associated serial port receive register does not contain valid, unread data. pcs 5/a1/pio3 peripheral chip select 5 (output, synchronous) latched address bit 1 (output, synchronous) pcs 5 this pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 5 is held high during a bus hold condition. it is also held high during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a1 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. during a bus hold condition, a1 retains its previously latched value. pcs 6/a2/pio2 peripheral chip select 6 (output, synchronous) latched address bit 2 (output, synchronous) pcs 6 this pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 6 is held high during a bus hold condition or reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a2 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. during a bus hold condition, a2 retains its previously latched value. pio31Cpio0 (shared) programmable i/o pins (input/output, asynchronous, open-drain) the am186es and am188es microcontrollers provide 32 individually programmable i/o pins. each pio can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. the pins that are multiplexed with pio31Cpio0 are listed in table 2 and table 3. after power-on reset, the pio pins default to various configurations. the column titled power-on reset status in table 2 and table 3 lists the defaults for the pios. most of the pio pins are configured as pio inputs with pullup after power-on reset. the system initialization code must reconfigure any pio pins as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset.
34 am186/188es and am186/188eslv microcontrollers preliminary table 2. numeric pio pin designations table 3. alphabetic pio pin designations notes: the following notes apply to both tables. 1. these pins are used by emulators. (emulators also use s 2Cs 0, res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0.) 2. these pins revert to normal operation if bhe / aden (186) or rfsh 2/aden (188) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2pcs 6/a2 input with pullup 3pcs 5/a1 input with pullup 4 dt/r normal operation (3) 5den /ds normal operation (3) 6 srdy normal operation (4) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0/int5 input with pullup 13 drq1/int6 input with pullup 14 mcs 0 input with pullup 15 mcs 1 input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2/cts 1/enrx 1 input with pullup 19 pcs 3/rts 1/rtr 1 input with pullup 20 rts 0/rtr 0 input with pullup 21 cts 0/enrx 0 input with pullup 22 txd0 input with pullup 23 rxd0 input with pullup 24 mcs 2 input with pullup 25 mcs 3/rfsh input with pullup 26 (1,2) uzi input with pullup 27 txd1 input with pullup 28 rxd1 input with pullup 29 (1,2) s6/lock /clkdiv 2 input with pullup 30 int4 input with pullup 31 int2/inta 0/pwd input with pullup associated pin pio no power-on reset status a17 (1) 7 normal operation (3) a18 (1) 8 normal operation (3) a19 (1) 9 normal operation (3) cts 0/enrx 0 21 input with pullup den /ds 5 normal operation (3) drq0/int5 12 input with pullup drq1/int6 13 input with pullup dt/r 4 normal operation (3) int2/inta 0/pwd 31 input with pullup int4 30 input with pullup mcs 0 14 input with pullup mcs 1 15 input with pullup mcs 2 24 input with pullup mcs 3/rfsh 25 input with pullup pcs 0 16 input with pullup pcs 1 17 input with pullup pcs 2/cts 1/enrx 1 18 input with pullup pcs 3/rts 1/rtr 1 19 input with pullup pcs 5/a1 3 input with pullup pcs 6/a2 2 input with pullup rts 0/rtr 0 20 input with pullup rxd0 23 input with pullup rxd1 28 input with pullup s6/lock /clkdiv 2 (1,2) 29 input with pullup srdy 6 normal operation (4) tmrin0 11 input with pullup tmrin1 0 input with pullup tmrout0 10 input with pulldown tmrout1 1 input with pulldown txd0 22 input with pullup txd1 27 input with pullup uzi (1,2) 26 input with pullup
am186/188es and am186/188eslv microcontrollers 35 preliminary rd read strobe (output, synchronous, three-state) rd this pin indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guaranteed to not be asserted before the address and data bus is floated during the address-to- data transition. rd floats during a bus hold condition. res reset (input, asynchronous, level-sensitive) this pin requires the microcontroller to perform a reset. when res is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers cpu control to the reset address, ffff0h. res must be held low for at least 1 ms. res can be asserted asynchronously to clkouta because res is synchronized internally. for proper initialization, v cc must be within specifications, and clkouta must be stable for more than four clkouta periods during which res is asserted. the microcontroller begins fetching instructions approximately 6.5 clkouta periods after res is deasserted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network. rfsh 2/aden (am188es microcontroller only) refresh 2 (three-state, output, synchronous) address enable (input, internal pullup) rfsh 2 asserted low to signify a dram refresh bus cycle. the use of rfsh 2/aden to signal a refresh is not valid when psram mode is selected. instead, the mcs 3/rfsh signal is provided to the psram. aden if rfsh 2/aden is held high or left floating on power-on reset, the ad bus (ao15Cao8 and ad7C ad0) is enabled or disabled during the address portion of lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory address is accessed on the a19Ca0 pins. this mode of operation reduces power consumption. for more information, see the bus operation section on page 39. there is a weak internal pullup resistor on rfsh 2/aden so no external pullup is required. if rfsh 2/aden is held low on power-on reset, the ad bus drives both addresses and data, regardless of the da bit setting. the pin is sampled one crystal clock cycle after the rising edge of res . rfsh 2/aden is three-stated during bus holds and once mode. rts 0/rtr 0/pio20 ready-to-send 0 (output, asynchronous) ready-to-receive 0 (output, asynchronous) rts 0 this pin provides the ready to send signal for asynchronous serial port 0 when the rts 0 bit in the auxcon register is 1 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the rts 0 signal is asserted when the associated serial port transmit register contains data that has not been transmitted. rtr 0 this pin provides the ready to receive signal for asynchronous serial port 0 when the rts 0 bit in the auxcon register is 0 and hardware flow control is enabled for the port (fc bit in the serial port 0 control register is set). the rtr 0 signal is asserted when the associated serial port receive register does not contain valid, unread data. rxd0/pio23 receive data 0 (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port 0. rxd1/pio28 receive data 1 (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port 1. s 2Cs 0 bus cycle status (output, three-state, synchronous) these pins indicate to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/ o indicator, and s 1 can be used as a data transmit or receive indicator. s 2Cs 0 float during bus hold and hold acknowledge conditions. the s 2Cs 0 pins are encoded as shown in table 4. table 4. bus cycle encoding s 2s 1s 0 bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 011halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 111none (passive)
36 am186/188es and am186/188eslv microcontrollers preliminary s6/lock /clkdiv 2/pio29 bus cycle status bit 6 (output, synchronous) bus lock (output, synchronous) clock divide by 2 (input, internal pullup) s6 during the second and remaining periods of a cycle (t 2 , t 3 , and t 4 ), this pin is asserted high to indicate a dma-initiated bus cycle. during a bus hold or reset condition, s6 floats. lock this signal is asserted low to indicate to other system bus masters that they are not to gain control of the system bus. this signal is only available during t 1 . lock on the am186es and am188es microcontrollers does not conform to the timing of the lock signal on the 80c186/188 microcontrollers. this signal is primarily intended for use by emulators. clkdiv 2 if s6/clkdiv 2/pio29 is held low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. if this mode is selected, the pll is disabled. the pin is sampled on the rising edge of res . if s6 is to be used as pio29 in input mode, the device driving pio29 must not drive the pin low during power- on reset. s6/clkdiv 2/pio29 defaults to a pio input with pullup, so the pin does not need to be driven high externally. srdy/pio6 synchronous ready (input, synchronous, level-sensitive) this pin indicates to the microcontroller that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkouta. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to always assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. tmrin0/pio11 timer input 0 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 0. after internally synchronizing a low-to-high transition on tmrin0, the microcontroller increments the timer. tmrin0 must be tied high if not being used. when pio11 is enabled, tmrin0 is pulled high internally. tmrin0 is driven internally by int2/inta 0/pwd when pulse width demodulation mode is enabled. the tmrin0/pio11 pin can be used as a pio when pulse width demodulation mode is enabled. tmrin1/pio0 timer input 1 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 1. after internally synchronizing a low-to-high transition on tmrin1, the microcontroller increments the timer. tmrin1 must be tied high if not being used. when pio0 is enabled, tmrin1 is pulled high internally. tmrin1 is driven internally by int2/inta 0/pwd when pulse width demodulation mode is enabled. the tmrin1/pio0 pin can be used as a pio when pulse width demodulation mode is enabled. tmrout0/pio10 timer output 0 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout0 is floated during a bus hold or reset. tmrout1/pio1 timer output 1 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout1 floats during a bus hold or reset. txd0/pio22 transmit data 0 (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port 0. txd1/pio27 transmit data 1 (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port 1. ucs /once 1 upper memory chip select (output, synchronous) once mode request 1 (input, internal pullup) ucs this pin indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is held high during a bus hold condition. after reset, ucs is active for the 64 kbyte memory range from f0000h to fffffh, including the reset address of ffff0h. once 1 during reset, this pin and lcs /once 0 indi- cate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the ris- ing edge of res . if both pins are asserted low, the mi- crocontroller enters once mode. otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the micro-
am186/188es and am186/188eslv microcontrollers 37 preliminary controller does not inadvertently enter once mode, once 1 has a weak internal pullup resistor that is ac- tive only during a reset. this pin is not three-stated dur- ing a bus hold condition. uzi /pio26 upper zero indicate (output, synchronous) this pin lets the designer determine if an access to the interrupt vector table is in progress by oring it with bits 15C10 of the address and data bus (ad15Cad10 on the 186 and ao15Cao10 on the 188). uzi is the logical or of the inverted a19Ca16 bits. it asserts in the first period of a bus cycle and is held throughout the cycle. this pin should be allowed to float or it should be pulled high at reset. this pin has an internal pullup. if this pin is low at the negation of reset, the am186es and am188es microcontrollers will enter a reserved clock test mode. v cc power supply (input) these pins supply power (+5 v) to the microcontroller. whb (am186es microcontroller only) write high byte (output, three-state, synchronous) this pin and wlb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical or of bhe and wr . this pin floats during reset. wlb (am186es microcontroller only) wb (am188es microcontroller only) write low byte (output, three-state, synchronous) write byte (output, three-state, synchronous) wlb this pin and whb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 microcontroller designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. wlb is asserted with ad7Cad0. wlb is the logical or of ad0 and wr . this pin floats during reset. wb on the am188es microcontroller, this pin indicates a write to the bus. wb uses the same early timing as the nonmultiplexed address bus. wb is associated with ad7Cad0. this pin floats during reset. wr write strobe (output, synchronous) wr this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. wr floats during a bus hold or reset condition. x1 crystal input (input) this pin and the x2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, connect the source to the x1 pin and leave the x2 pin unconnected. x2 crystal output (output) this pin and the x1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, leave the x2 pin unconnected and connect the source to the x1 pin.
38 am186/188es and am186/188eslv microcontrollers preliminary functional description the am186es and am188es microcontrollers are based on the architecture of the original am186 and am188 microcontrollersthe 80c186 and 80c188 mi- crocontrollers. the am186es and am188es micro- controllers function in the enhanced mode of earlier generations of am186 and am188 microcontrollers. enhanced mode includes system features such as power-save control. each of the 8086, 8088, 80186, and 80188 microcon- trollers contains the same basic set of registers, in- structions, and addressing modes. the am186es and am188es microcontrollers are backward compatible with the 80c186 and 80c188 microcontrollers. a full description of all the am186es and am188es mi- crocontroller registers and instructions is included in the am186es and am188es microcontrollers users manual , order# 21096. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of 64k (216) 8-bit bytes. memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, ss, or es). the physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see fig- ure 3). this allows for a 1-mbyte physical address size. all instructions that address operands in memory must specify the segment value and the 16-bit offset value. for speed and compact instruction encoding, the seg- ment register used for physical address generation is implied by the addressing mode used (see table 5). figure 3. two-component address i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions (in, ins and out, outs) ad- dress the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero-ex- tended such that a15Ca8 are low. i/o port addresses 00f8h through 00ffh are reserved. table 5. segment register selection rules 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memory 15 0 19 0 19 0 15 0 15 0 offset memory reference needed segment register used implicit segment selection rule instructions code (cs) instructions (including immediate data) local data data (ds) all data references stack stack (ss) all stack pushes and pops; any memory references that use bp register external data (global) extra (es) all string instruction references that use the di register as an index
am186/188es and am186/188eslv microcontrollers 39 preliminary bus operation the industry-standard 80c186 and 80c188 microcon- trollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t1 clock phase. the am186es and am188es micro- controllers continue to provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t1Ct4). for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus on the am186es microcontroller and on the ad and ao buses on the am188es microcontroller during the normal address portion of the bus cycle for accesses to ucs and/or lcs address spaces. in this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the umcs and lmcs registers. when address disable is in effect, the number of signals that assert on the bus during all nor- mal bus cycles to the associated address space is re- duced, decreasing power consumption and reducing processor switching noise. on the am188es micro- controller, the address is driven on a015Ca08 during the data portion of the bus cycle regardless of the set- ting of the da bits. if the aden pin is pulled low during processor reset, the value of the da bits in the umcs and lmcs regis- ters is ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed ad- dress bus and providing support for existing emulation tools. the following diagrams show the am186es and am188es microcontroller bus cycles when the ad- dress bus disable feature is in effect: n figure 4 shows the affected signals during a normal read or write operation for an am186es microcon- troller. the address and data are multiplexed onto the ad bus. n figure 5 shows an am186es microcontroller bus cycle when address bus disable is in effect. this re- sults in the ad bus operating in a nonmultiplexed address/data mode. the a bus has the address during a read or write operation. n figure 6 shows the affected signals during a normal read or write operation for an am188es microcon- troller. the multiplexed address/data mode is com- patible with the 80c186 and 80c188 microcontrollers and might be used to take advan- tage of existing logic or peripherals. n figure 7 shows an am188es microcontroller bus cycle when address bus disable is in effect. the ad- dress and data is not multiplexed. the ad7Cad0 signals have only data on the bus, while the ao bus has the address during a read or write operation. figure 4. am186es microcontroller address busnormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (read) data ad15Cad0 (write) lcs or ucs address data address address phase data phase a19Ca0 address mcs x, pcs x
40 am186/188es and am186/188eslv microcontrollers preliminary figure 5. am186es microcontrollerread and write with address bus disable in effect figure 6. am188es microcontroller address busnormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs , ucs ad15Cad0 (read) address phase data data phase a19Ca0 address mcs x, pcs x clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data ao15Cao8 (read or write) ad7Cad0 (write) address address data address address phase data phase a19Ca0 address lcs or ucs mcs x, pcs x
am186/188es and am186/188eslv microcontrollers 41 preliminary figure 7. am188es microcontrollerread and write with address bus disable in effect bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory-mapped and i/o-mapped peripherals and the peripheral control block. the am186es and am188es microcontrollers provide an enhanced bus interface unit with the following features: n a nonmultiplexed address bus n on the am186es microcontroller, a static bus-siz- ing option for 8-bit and 16-bit memory and i/o n separate byte write enables for high and low bytes in the am186es microcontroller only n pseudo static ram (psram) support the standard 80c186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. on the am186es and am188es microcontrollers, new byte write enables, psram control logic, and a new nonmultiplexed ad- dress bus can reduce design costs by eliminating this external logic. nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one- half clkouta cycle in advance of the address on the ad bus. when used in conjunction with the modified ucs and lcs outputs and the byte-write enable sig- nals, the a19Ca0 bus provides a seamless interface to sram, psram, and flash eprom memory systems. static bus sizing the 80c186 microcontroller provided a 16-bit wide data bus over its entire address range, memory, and i/o, but did not allow accesses to an 8-bit wide bus. the 80c188 microcontroller provided a lower-cost in- terface by reducing the data bus width to 8 bits, again over the entire address range. the am188es micro- controller follows the 80c188 microcontroller in provid- ing an 8-bit data bus to all memory and peripherals. however, the am186es microcontroller differs from the 80c186 microcontroller in allowing programmabil- ity for data bus widths through fields in the auxiliary configuration (auxcon) register, as shown in table 6. the width of the data access should not be modified while the processor is fetching instructions from the as- sociated address space. clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data address ao15Cao8 lcs , ucs ad7Cad0 (write) data address phase data phase a19Ca0 address mcs x, pcs x
42 am186/188es and am186/188eslv microcontrollers preliminary table 6. programming am186es microcontroller bus width byte-write enables the am186es microcontroller provides the whb (write high byte) and wlb (write low byte) signals, which act as byte-write enables. whb is the logical or of bhe and wr . whb is low when bhe and wr are both low. wlb is the logical or of a0 and wr . wlb is low when a0 and wr are both low. wb is low whenever a byte is written on the am188es microcontroller. on the am188es microcontroller, the wb (write byte) pin indicates a write to the bus. wb uses the same early timing as the nonmulitplexed address bus. wb is associated with ad7C-ad0. this pin floats during reset. the byte-write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common srams. pseudo static ram (psram) support the am186es and am188es microcontrollers support the use of psram devices in low memory chip-select (lcs) space only. when psram mode is enabled, the timing for the lcs signal is modified by the chip-select control unit to provide a cs precharge period during psram accesses. the 40-mhz timing of the am186es and am188es microcontrollers is appropri- ate to allow 70-ns psram to run with one wait state. psram mode is enabled through a bit in the low mem- ory chip-select (lmcs) register. the psram feature is disabled on cpu reset. in addition to the lcs timing changes for psram pre- charge, the psram devices also require periodic re- fresh of all internal row addresses to retain their data. although refresh of psram can be accomplished sev- eral ways, the am186es and am188es microcontrol- lers implement auto refresh only. the am186es and am188es microcontrollers gener- ate a refresh signal, rfsh , to the psram devices when psram mode and the refresh control unit are enabled. no refresh address is required by the psram when using the auto refresh mechanism. the rfsh signal is multiplexed with the mcs 3 signal pin. when psram mode is enabled, mcs 3 is not available for use as a chip-select signal. the refresh control unit must be programmed before accessing psram in lcs space. the refresh counter in the clock prescaler (cdram) register must be con- figured with the required refresh interval value. the ending address of lcs space and the ready and wait- state generation in the lmcs register must also be pro- grammed. the refresh counter reload value in the cdram register should not be set to less than 18 (12h) in order to provide time for processor cycles within re- fresh. the refresh address counter must be set to 000000h to prevent another chip select from asserting. lcs is held high during a refresh cycle. the a bus is not used during refresh cycles. the lmcs register must be configured to external ready ignored (r2=1) with one wait state (r1Cr0=01b), and the psram mode enable bit (pse) must be set to 1. peripheral control block (pcb) the integrated peripherals of the am186es and am188es microcontrollers are controlled by 16-bit read/write registers. the peripheral registers are con- tained within an internal 256-byte control block. the registers are physically located in the peripheral de- vices they control, but they are addressed as a single 256-byte block. table 7 shows a map of these regis- ters. reading and writing the pcb code that is intended to execute on the am188es mi- crocontroller should perform all writes to the pcb reg- isters as byte writes. these writes transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruction. for example, out dx, al results in the value of ax being written to the port address in dx. reads to the pcb should be done as word reads. code written in this manner runs correctly on the am188es microcontroller and on the am186es microcontroller. unaligned reads and writes to the pcb result in unpre- dictable behavior on both the am186es and am188es microcontrollers. for a complete description of all the registers in the pcb, see the am186es and am188es microcontrol- lers users manual , order# 21096. space auxcon field value bus width comments ucs C C 16 bits not configurable lcs lsiz 0 16 bits default 1 8 bits i/o iosiz 0 16 bits default 1 8 bits other msiz 0 16 bits default 1 8 bits
am186/188es and am186/188eslv microcontrollers 43 preliminary table 7. peripheral control block register map notes: 1. the register has been changed from the am186em and am188em microcontrollers. 2. the register is new. note: all unused addresses are reserved and should not be accessed. register name offset processor control registers: peripheral control block relocation register feh reset configuration register f6h processor release level register 1 f4h auxiliary configuration register 2 f2h system configuration register 1 f0h watchdog timer control register 2 e6h enable rcu register 1 e4h clock prescaler register e2h memory partition register e0h dma registers: dma 1 control register 1 dah dma 1 transfer count register d8h dma 1 destination address high register d6h dma 1 destination address low register d4h dma 1 source address high register d2h dma 1 source address low register d0h dma 0 control register 1 cah dma 0 transfer count register c8h dma 0 destination address high register c6h dma 0 destination address low register c4h dma 0 source address high register c2h dma 0 source address low register c0h chip-select registers: pcs and mcs auxiliary register a8h midrange memory chip-select register a6h peripheral chip-select register a4h low memory chip-select register 1 a2h upper memory chip-select register a0h serial port 0 registers: serial port 0 baud rate divisor register 1 88h serial port 0 receive register 1 86h serial port 0 transmit register 1 84h serial port 0 status register 1 82h serial port 0 control register 1 80h pio registers: pio data 1 register 7ah pio direction 1 register 78h pio mode 1 register 76h pio data 0 register 74h pio direction 0 register 72h pio mode 0 register 70h timer registers: timer 2 mode/control register 66h timer 2 max count compare a register 62h timer 2 count register 60h timer 1 mode/control register 5eh timer 1 max count compare b register 5ch timer 1 max count compare a register 5ah timer 1 count register 58h timer 0 mode/control register 56h timer 0 max count compare b register 54h timer 0 max count compare a register 52h timer 0 count register 50h interrupt registers: serial port 0 interrupt control register 1 44h serial port 1 interrupt control register 2 42h int4 interrupt control register 40h int3 control register 3eh int2 control register 3ch int1 control register 3ah int0 control register 38h dma1/int6 interrupt control register 1 36h dma0/int5 interrupt control register 1 34h timer interrupt control register 32h interrupt status register 30h interrupt request register 1 2eh interrupt in-service register 1 2ch interrupt priority mask register 2ah interrupt mask register 1 28h interrupt poll status register 26h interrupt poll register 24h end-of-interrupt register 22h interrupt vector register 20h serial port 1 registers: serial port 1 baud rate divisor register 2 18h serial port 1 receive register 2 16h serial port 1 transmit register 2 14h serial port 1 status register 2 12h serial port 1 control register 2 10h register name offset
44 am186/188es and am186/188eslv microcontrollers preliminary clock and power management the clock and power management unit of the am186es and am188es microcontrollers includes a phase-locked loop (pll) and a second programmable system clock output (clkoutb). phase-locked loop (pll) in a traditional 80c186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. because of the internal pll on the am186es and am188es microcontrollers, the internal clock gen- erated by the am186es and am188es microcontrol- lers (clkouta) is the same frequency as the crystal. the pll takes the crystal inputs (x1 and x2) and gen- erates a 45C55% (worst case) duty cycle intermediate system clock of the same frequency. this removes the need for an external 2x oscillator, reducing system cost. the pll is reset during power-on reset by an on- chip power-on reset (por) circuit. crystal-driven clock source the internal oscillator circuit of the am186es and am188es microcontrollers is designed to function with a parallel resonant fundamental or third overtone crys- tal. because of the pll, the crystal frequency should be equal to the processor frequency. do not replace a crystal with an lc or rc equivalent. the signals x1 and x2 are connected to an internal in- verting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (figure 8). in such a positive feedback circuit, the inverting amplifier has an output signal (x2) 180 de- grees out of phase of the input signal (x1). the external feedback network provides an additional 180-degree phase shift. in an ideal system, the input to x1 will have 360 or zero degrees of phase shift. the ex- ternal feedback network is designed to be as close to ideal as possible. if the feedback network is not provid- ing necessary phase shift, negative feedback dampens the output of the amplifier and negatively affects the op- eration of the clock generator. values for the loading on x1 and x2 must be chosen to provide the necessary phase shift and crystal operation. selecting a crystal when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause vari- ance in the oscillation frequency from the desired spec- ified value (resonance). the load capacitance and the loading of the feedback network have the following re- lationship: where c s is the stray capacitance of the circuit. placing the crystal and c l in series across the inverting ampli- fier and tuning these values (c 1 , c 2 ) allows the crystal to oscillate at resonance. this relationship is true for both fundamental and third-overtone operation. finally, there is a relationship between c 1 and c 2 . to enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (x2). equal values of these loads tend to balance the poles of the inverting amplifier. the characteristics of the inverting amplifier set limits on the following parameters for crystals: esr (equivalent series resistance) ......40 w max drive level ..............................................1 mw max the recommended range of values for c 1 and c 2 are as follows: c 1 ..................................................................15 pf 20% c 2 ..................................................................22 pf 20% the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteris- tics of the chosen crystal and board design. figure 8. am186es and am188es microcontrollers oscillator configurations (c 1 c 2 ) (c 1 + c 2 ) c l = + c s crystal am186es 200 pf note 1 note 1 : use for third overtone mode xtal frequency l1 value (max) 20 mhz 12 m h 20% 25 mhz 8.2 m h 20% 33 mhz 4.7 m h 20% 40 mhz 3.0 m h 20% x1 x2 b. crystal configuration a. inverting amplifier configuration c 1 c 2 crystal c 1 c 2 microcontroller
am186/188es and am186/188eslv microcontrollers 45 preliminary external source clock alternately, the internal oscillator can be driven from an external clock source. this source should be con- nected to the input of the inverting amplifier (x1), with the output (x2) not connected. system clocks the base system clock of amds original 80c186 and 80c188 microcontrollers is renamed clkouta and the additional output is called clkoutb. clkouta and clkoutb operate at either the processor fre- quency or the pll frequency. the output drivers for both clocks are individually programmable for disable. figure 9 shows the organization of the clocks. the second clock output (clkoutb) allows one clock to run at the pll frequency and the other clock to run at the power-save frequency. individual drive enable bits allow selective enabling of just one or both of these clock outputs. power-save operation the power-save mode of the am186es and am188es microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. in power-save mode, operation of the cpu and internal peripherals continues at a slower clock fre- quency. when an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clocks next rising edge of t 3 . note: power-save operation requires that clock-de- pendent devices be reprogrammed for clock frequency changes. software drivers must be aware of clock fre- quency. initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res must be held low for 1 ms during power-up to ensure proper device ini- tialization. res forces the am186es and am188es microcontrollers to terminate all execution and local bus activity. no instruction or bus activity occurs as long as res is active. after res becomes inactive and an internal processing interval elapses, the microcontrol- ler begins execution with the instruction at physical lo- cation ffff0h, with ucs asserted with three wait states. res also sets some registers to predefined val- ues and resets the watchdog timer. the reset configuration register when the res input is asserted low, the contents of the address/data bus (ad15Cad0) are written into the reset configuration register. the system can place con- figuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. the pro- cessor does not drive the address/data bus during re- set. for example, the reset configuration register could be used to provide the software with the position of a con- figuration switch in the system. using weak external pullup and pulldown resistors on the address and data bus, the system can provide the microcontroller with a value corresponding to the position of the jumper dur- ing a reset. figure 9. clock organization pll power-save divisor (/2 to /128) mux clkouta clkoutb drive enable drive enable x1, x2 processor internal clock time delay 6 2.5ns mux
46 am186/188es and am186/188eslv microcontrollers preliminary chip-select unit the am186es and am188es microcontrollers contain logic that provides programmable chip-select genera- tion for both memories and peripherals. the logic can be programmed to provide ready and wait-state gener- ation and latched address bits a1 and a2. the chip-se- lect lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. the am186es and am188es microcontrollers provide six chip-select outputs for use with memory devices and six more for use with peripherals in either memory space or i/o space. the six memory chip selects can be used to address three memory ranges. each periph- eral chip select addresses a 256-byte block that is off- set from a programmable base address. a write to a chip select register will enable the corresponding chip select logic even if the actual pin has another function (e.g., pio). chip-select timing the timing for the ucs and lcs outputs is modified from the original 80c186 microcontroller. these out- puts now assert in conjunction with the nonmultiplexed address bus for normal memory timing. to allow these outputs to be available earlier in the bus cycle, the num- ber of programmable memory size selections has been reduced. ready and wait-state programming the am186es and am188es microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. the ready sig- nal can be either the ardy or srdy signal. each chip- select control register (umcs, lmcs, mmcs, pacs, and mpcs) contains a single-bit field that determines whether the external ready signal is required or ignored. the number of wait states to be inserted for each ac- cess to a peripheral or memory region is programma- ble. the chip-select control registers for ucs , lcs , mcs 3Cmcs 0, pcs 6, and pcs 5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. pcs 3Cpcs 0 use three bits to pro- vide additional values of 5, 7, 9, and 15 wait states. when external ready is required, internally pro- grammed wait states will always complete before exter- nal ready can terminate or extend a bus cycle. for example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. if external ready is as- serted at that time, the access completes after six cy- cles (four cycles plus two wait states). if external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, and one more wait state occurs followed by t 4 . the ardy signal on the am186es and am188es mi- crocontrollers is a true asynchronous ready signal. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. if the falling edge of ardy is not synchronized to clkouta as specified, an additional clock period may be added. chip-select overlap although programming the various chip selects on the am186es microcontroller so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some sys- tems. in such systems, the chip selects whose asser- tions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. the peripheral control block (pcb) is accessed using internal signals. these internal signals function as chip selects configured with zero wait states and no external ready. therefore, the pcb can be programmed to ad- dresses that overlap external chip-select signals only if those external chip selects are programmed to zero wait states with no external ready required. when overlapping an additional chip select with either the lcs or ucs chip selects, it must be noted that set- ting the disable address (da) bit in the lmcs or umcs register disables the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip-select pins can be configured as either chip selects (normal function) or as pio inputs or outputs. it should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip se- lects or pios. this means that if these chip selects are enabled (by a write to the mmcs and mpcs for the mcs chip selects, or by a write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. although the pcs 4 signal is not available on an exter- nal pin, the ready and wait state logic for this signal still exists internal to the part. for this reason, the pcs 4 ad- dress space must follow the rules for overlapping chip selects. the ready and wait-state logic for pcs 6C pcs 5 is disabled when these signals are configured as address bits a2Ca1. failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting
am186/188es and am186/188eslv microcontrollers 47 preliminary for a ready signal. this behavior may occur even in a system in which ready is always asserted (ardy or srdy tied high). configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not con- sidered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. upper memory chip select the am186es and am188es microcontrollers provide a ucs chip select for the top of memory. on reset the am186es and am188es microcontrollers begin fetch- ing and executing instructions at memory location ffff0h. therefore, upper memory is usually used as instruction memory. to facilitate this usage, ucs de- faults to active on reset, with a default memory range of 64 kbytes from f0000h to fffffh, with external ready required and three wait states automatically inserted. the ucs memory range always ends at fffffh. the ucs lower boundary is programmable. low memory chip select the am186es and am188es microcontrollers provide an lcs chip select for lower memory. the auxcon register can be used to configure lcs for 8-bit or 16-bit accesses. since the interrupt vector table is located at the bottom of memory starting at 00000h, the lcs pin is usually used to control data memory. the lcs pin is not active on reset. midrange memory chip selects the am186es and am188es microcontrollers provide four chip selects, mcs 3Cmcs 0, for use in a user-locat- able memory block. with some exceptions, the base address of the memory block can be located anywhere within the 1-mbyte memory address space of the am186es and am188es microcontrollers. the areas associated with the ucs and lcs chip selects are ex- cluded. if they are mapped to memory, the address range of the peripheral chip selects, pcs 6, pcs 5, and pcs 3Cpcs 0, are also excluded. the mcs address range can overlap the pcs address range if the pcs chip selects are mapped to i/o space. mcs 0 can be configured to be asserted for the entire mcs range. when configured in this mode, the mcs 3C mcs 1 pins can be used as pios. the auxcon register can be used to configure mcs for 8-bit or 16-bit accesses. the bus width of the mcs range is determined by the width of the non-ucs/non- lcs memory range. unlike the ucs and lcs chip selects, the mcs outputs assert with the same timing as the multiplexed ad ad- dress bus. peripheral chip selects the am186es and am188es microcontrollers provide six chip selects, pcs 6Cpcs 5 and pcs 3Cpcs 0, for use within a user-configured memory or i/o block. pcs 4 is not available on the am186es and am188es microcontrollers. the base address of the memory block can be located anywhere within the 1-mbyte memory address space, exclusive of the areas associ- ated with the ucs , lcs , and mcs chip selects, or they can be configured to access the 64-kbyte i/o space. the pcs pins are not active on reset. pcs 6Cpcs 5 can be programmed for zero to three wait states. pcs 3C pcs 0 can be programmed for four additional wait-state values: 5, 7, 9, and 15. the auxcon register can be used to configure pcs for 8-bit or 16-bit accesses. the bus width of the pcs range is determined by the width of the non-ucs/non- lcs memory range or by the width of the i/o area. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186/188 microcon- trollers. refresh control unit the refresh control unit (rcu) automatically gener- ates refresh bus cycles. after a programmable period of time, the rcu generates a memory read request to the bus interface unit. the rcu is fixed to three wait states for the psram auto refresh mode. in the am186es and am188es microcontrollers, re- fresh is enabled when the ena bit is set in the enable rcu register, offset e4h. this is different from the am186em and am188em microcontrollers where the psram enable bit in the low memory chip-select reg- ister, offset a2h, enables refresh. the refresh function is the same as on the am186em and am188em micro- controllers, except that the dram address is not driven on dram refreshes. if the hlda pin is active when a refresh request is gen- erated (indicating a bus hold condition), the am186es and am188es microcontrollers deactivate the hlda pin in order to perform a refresh cycle. the external bus master must remove the hold signal for at least one clock in order to allow the refresh cycle to execute.
48 am186/188es and am186/188eslv microcontrollers preliminary interrupt control unit the am186es and am188es microcontrollers can re- ceive interrupt requests from a variety of sources, both internal and external. the internal interrupt controller arranges these requests by priority and presents them one at a time to the cpu. there are up to eight external interrupt sources on the am186es and am188es microcontrollersseven maskable interrupt pins and one nonmaskable interrupt (nmi) pin. in addition, there are eight internal interrupt sources (three timers, two dma channels, the two asynchronous serial ports, and the watchdog timer nmi) that are not connected to external pins. int5 and int6 are multiplexed with drq0 and drq1. these two interrupts are available if the associated dma is not en- abled or is being used with internal synchronization. the am186es and am188es microcontrollers provide up to six interrupt sources not present on the 80c186 and 80c188 microcontrollers. there are up to three ad- ditional external interrupt pinsint4, int5, and int6. these pins operate much like the int3Cint0 interrupt pins on the 80c186 and 80c188 microcontrollers. there are also two internal interrupts from the serial ports and the watchdog timer can generate interrupts. the seven maskable interrupt request pins can be used as direct interrupt requests. int4Cint0 can be ei- ther edge triggered or level triggered. int6 and int5 are edge triggered only. in addition, int0 and int1 can be configured in cascade mode for use with an external 82c59a-compatible interrupt controller. when int0 is configured in cascade mode, the int2 pin is automati- cally configured in its inta 0 function. when int1 is configured in cascade mode, the int3 pin is automati- cally configured in its inta 1 function. an external inter- rupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. int6Cint4 are not available in slave mode. interrupts are automatically disabled when an interrupt is taken. interrupt-service routines (isrs) may re-enable interrupts by setting the if flag. this allows interrupts of greater or equal priority to interrupt the currently executing isr. interrupts from the same source are disabled as long as the corresponding bit in the interrupt in-service register is set. int1 and int0 provide a special bit to enable special fully nested mode. when configured in special fully nested mode, the interrupt source may generate a new interrupt regardless of the setting of the in-service bit. timer control unit there are three 16-bit programmable timers and a watchdog timer on the am186es and am188es micro- controllers. timer 0 and timer 1 are connected to four external pins (each one has an input and an output). these two tim- ers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle wave- forms. when pulse width demodulation is enabled, timer 0 and timer 1 are used to measure the width of the high and low pulses on the pwd pin. (see the pulse width demodulation section on page 51.) timer 2 is not connected to any external pins. it can be used for real-time coding and time-delay applications. it can also be used as a prescaler to timers 0 and 1 or to synchronize dma transfers. the programmable timers are controlled by eleven 16- bit registers in the peripheral control block. a timers timer-count register contains the current value of that timer. the timer-count register can be read or written with a value at any time, whether the timer is running or not. the microcontroller increments the value of the timer-count register each time a timer event occurs. each timer also has a maximum-count register that de- fines the maximum value the timer can reach. when the timer reaches the maximum value, it resets to 0 during the same clock cycle. the value in the maxi- mum-count register is never stored in the timer-count register. also, timers 0 and 1 have a secondary maxi- mum-count register. using both the primary and sec- ondary maximum-count registers lets the timer alternate between two maximum values. if the timer is programmed to use only the primary max- imum-count register, the timer output pin switches low for one clock cycle after the maximum value is reached. if the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. the duty cycle of the waveform depends on the values in the maximum- count registers. each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter of the internal clock frequency. a timer can be clocked exter- nally at this same frequency; however, because of in- ternal synchronization and pipelining of the timer circuitry, the timer output can take up to six clock cycles to respond to the clock or gate input.
am186/188es and am186/188eslv microcontrollers 49 preliminary watchdog timer the am186es and am188es microcontrollers provide a true watchdog timer function. the watchdog timer (wdt) can be used to regain control of the system when software fails to respond as expected. the wdt is active after reset. it can only be modified a single time by a keyed sequence of writes to the watchdog timer control register (wdtcon) following reset. this single write can either disable the timer or modify the timeout period and the action taken upon timeout. a keyed sequence is also required to reset the current wdt count. this behavior ensures that randomly exe- cuting code will not prevent a wdt event from occur- ring. the wdt supports up to a 1.67-second timeout period in a 40-mhz system. after reset, the wdt is enabled and the timeout period is set to its maximum value. the wdt can be configured to cause either an nmi in- terrupt or a system reset upon timeout. if the wdt is configured for nmi, the nmiflag in the wdtcon reg- ister is set when the nmi is generated. the nmi inter- rupt service routine (isr) should examine this flag to determine if the interrupt was generated by the wdt or by an external source. if the nmiflag is set, the isr should clear the flag by writing the correct keyed se- quence to the wdtcon register. if the nmiflag is set when a second wdt timeout occurs, a wdt system reset is generated rather than a second nmi event. when the processor takes a wdt reset, either due to a single wdt event with the wdt configured to gener- ate resets or due to a wdt event with the nmiflag set, the rstflag in the wdtcon register is set. this allows system initialization code to differentiate be- tween a hardware reset and a wdt reset and take ap- propriate action. the rstflag is cleared when the wdtcon register is read or written. the processor does not resample external pins during a wdt reset. this means that the clocking, the reset configuration register, and any other features that are user-select- able during reset do not change when a wdt system reset occurs. all other activities are identical to those of a normal system reset. note: the watchdog timer (wdt) is active after re- set. direct memory access (dma) direct memory access (dma) permits transfer of data between memory and peripherals without cpu involve- ment. the dma unit in the am186es and am188es microcontrollers, shown in figure 10, provides two high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory to memory or i/o to i/o). the dma channels can be directly con- nected to the asynchronous serial ports. either bytes or words can be transferred to or from even or odd addresses on the am186es microcon- troller. however, the am186es microcontroller does not support word dma transfers to or from memory configured for 8-bit accesses. the am188es micro- controller does not support word transfers. only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. each channel accepts a dma request from one of four sources: the channel request pin (drq1Cdrq0), timer 2, a serial port, or the system software. the channels can be programmed with different priorities in the event of a simultaneous dma request or if there is a need to interrupt transfers on the other channel. dma operation each channel has six registers in the peripheral control block that define specific channel operations. the dma registers consist of a 20-bit source address (two regis- ters), a 20-bit destination address (two registers), a 16- bit transfer count register, and a 16-bit control register. the dma transfer count register (dtc) specifies the number of dma transfers to be performed. up to 64k of byte or word transfers can be performed with auto- matic termination. the dma control registers define the channel operation. all registers can be modified dur- ing any dma activity. any changes made to the dma registers are reflected immediately in dma operation. table 8. am186es microcontroller maximum dma transfer rates type of synchronization selected maximum dma transfer rate (mbytes) 40 mhz 33 mhz 25 mhz 20 mhz unsynchronized 10 8.25 6.25 5 source synch 10 8.25 6.25 5 destination synch (cpu needs bus) 6.6 5.5 4.16 3.3 destination synch (cpu does not need bus) 8 6.6 5 4
50 am186/188es and am186/188eslv microcontrollers preliminary figure 10. dma unit block diagram dma channel control registers each dma control register determines the mode of op- eration for the particular dma channel. the dma con- trol registers specify the following: n the mode of synchronization n whether bytes or words are transferred n whether an interrupt is generated after the last transfer n whether the drq pins are configured as int pins n whether dma activity ceases after a programmed number of dma cycles n the relative priority of the dma channel with re- spect to the other dma channel n whether the source address is incremented, decre- mented, or maintained constant after each transfer n whether the source address addresses memory or i/o space n whether the destination address is incremented, decremented, or maintained constant after trans- fers n whether the destination address addresses mem- ory or i/o space dma priority the dma channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending. dma cycles always have priority over internal cpu cycles except between locked memory accesses or word accesses to odd memory locations. however, an external bus hold takes priority over an internal dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access memory during a dma cycle, interrupt latency time suffers during se- quences of continuous dma cycles. an nmi request, however, causes all internal dma activity to halt. this allows the cpu to respond quickly to the nmi request. source address ch. 1 source address ch. 0 20-bit adder/subtractor dma control logic request selection logic adder control logic 20 20 channel control register 1 channel control register 0 16 drq1/serial port drq0/serial port internal address/data bus timer request interrupt request transfer counter ch. 1 destination address ch. 1 destination address ch. 0 transfer counter ch. 0
am186/188es and am186/188eslv microcontrollers 51 preliminary pulse width demodulation for many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its high and low phases. the am186es and am188es microcontrollers provide a pulse-width demodulation (pwd) option to fulfill this need. the pwd bit in the system configuration register (syscon) enables the pwd option. please note that the am186es and am188es microcontrollers do not support analog-to- digital conversion. in pwd mode, tmrin0, tmrin1, int2, and int4 are configured internal to the microcontroller to support the detection of rising and falling edges on the pwd input pin (int2/inta 0/pwd) and to enable either timer 0 when the signal is high or timer 1 when the signal is low. the int4, tmrin0, and tmrin1 pins are not used in pwd mode and so are available for use as pios. the following diagram shows the behavior of a system for a typical waveform. the interrupt service routine (isr) for the int2 and int4 interrupts should examine the current count of the associated timer, timer 1 for int2 and timer 0 for int4, in order to determine the pulse width. the isr should then reset the timer count register in preparation for the next pulse. since the timers count at one quarter of the processor clock rate, this determines the maximum resolution that can be obtained. further, in applications where the pulse width may be short, it may be necessary to poll the int2 and int4 request bits in the interrupt request register in order to avoid the overhead involved in tak- ing and returning from an interrupt. overflow condi- tions, where the pulse width is greater than the maximum count of the timer, can be detected by mon- itoring the maximum count (mc) bit in the associated timer or by setting the int bit to enable timer interrupt requests. asynchronous serial ports the am186es and am188es microcontrollers provide two independent asynchronous serial ports. these ports provide full-duplex, bidirectional data transfer using several industry-standard communications pro- tocols. the serial ports can be used as sources or des- tinations of dma transfers. the asynchronous serial ports support the following features: n full-duplex operation n 7-bit, 8-bit, or 9-bit data transfers n odd, even, or no parity n one stop bit n two lengths of break characters n error detection parity errors framing errors overrun errors n hardware handshaking with the following select- able control signals: clear-to-send (cts ) enable-receiver-request (enrx ) ready-to-send (rts ) ready-to-receive (rtr ) n dma to and from the serial ports n separate maskable interrupts for each port n multidrop protocol (9-bit) support n independent baud rate generators n maximum baud rate of 1/16th of the cpu clock n double-buffered transmit and receive dma transfers through the serial port the am186es and am188es microcontrollers support dma transfers both to and from the serial port. either or both dma channels and either or both serial ports can be used for dma transmits or receives. see the dma control register descriptions in the am186es and am188es microcontrollers users manual for more in- formation. int2 int4 int2 ints generated tmr1 enabled tmr0 enabled
52 am186/188es and am186/188eslv microcontrollers preliminary programmable i/o (pio) pins there are 32 pins on the am186es and am188es mi- crocontrollers that are available as user-programmable i/o signals. table 2 on page 34 and table 3 on page 34 list the pio pins. each of these pins can be used as a user-programmable input or output signal if the normal shared function is not needed. if a pin is enabled to function as a pio signal, the pre- assigned signal function is disabled and does not affect the level on the pin. a pio signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 2 on page 34 and table 3 on page 34 lists the defaults for the pios. the system initialization code must reconfigure the pios as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. note that emulators use a19, a18, a17, s6, and uzi . in environments where an emulator is needed, these pins must be configured for normal functionnot as pios. if the ad15Cad0 bus override is enabled on power-on reset, then s6/clkdiv 2 and uzi revert to normal oper- ation instead of pio input with pullup. if bhe /aden (186) or rfsh 2/aden (188) is held low during power- on reset, the ad15Cad0 bus override is enabled.
am186/188es and am186/188eslv microcontrollers 53 preliminary absolute maximum ratings storage temperature am186es/am188es....................... C65 c to +125 c am186eslv/am188eslv .............. C65 c to +125 c voltage on any pin with respect to ground am186/188es ............................ C0.5 v to v cc +0.5 v am186/188eslv ....................... C0.5 v to v cc +0.5 v note: stresses above those listed under absolute maximum ratings may cause permanent device fail- ure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges operating ranges define those limits between which the functionality of the device is guaranteed. am186es/am188es microcontrollers commercial (t c ) .................................0 c to +100 c industrial* (t a ) ..................................C40 c to +85 c v cc up to 33 mhz......................................5 v 10% v cc greater than 33 mhz ............................5 v 5% am186eslv/am188eslv microcontrollers commercial (t a ) ................................... 0 c to +70 c v cc up to 25 mhz................................. 3.3 v 0.3 v where: t c = case temperature t a = ambient temperature *industrial versions of am186es and am188es microcontrollers are available in 20 and 25 mhz operating frequencies only. dc characteristics over commercial operating ranges notes: a the lcs /once 0, mcs 3Cmcs 0, ucs /once 1, and rd pins have weak internal pullup resistors. loading the lcs /once 0 and ucs /once 1 pins in excess of i oh = C200 m a during reset can cause the device to go into once mode. b current is measured with the device in reset with x1 and x2 driven and all other non-power pins open but held high or low. c testing is performed with the pins floating, either during hold or by invoking the once mode. d power supply current for the am186eslv and am188eslv microcontrollers, which are available in 20 and 25 mhz operating frequencies only. symbol parameter description test conditions preliminary unit min max v il input low voltage (except x1) C0.5 0.8 v v il 1 clock input low voltage (x1) C0.5 0.8 v v ih input high voltage (except res and x1) 2.0 v cc +0.5 v v ih 1 input high voltage (res )2.4v cc +0.5 v v ih 2 clock input high voltage (x1) v cc C0.8 v cc +0.5 v v ol output low voltage am186es and am188es i ol = 2.5 ma (s 2Cs 0) i ol = 2.0 ma (others) 0.45 v am186eslv and am188eslv i ol = 1.5 ma (s 2Cs 0) i ol = 1.0 ma (others) 0.45 v v oh output high voltage (a) am186es and am188es i oh = C2.4 ma @ 2.4 v 2.4 v cc +0.5 v i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v am186eslv and am188eslv i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v i cc power supply current @ 0 c am186es and am188es v cc = 5.5 v (b) 5.9 ma/mhz am186eslv and am188eslv v cc = 3.6 v (b) 2.75 ma/mhz i li input leakage current @ 0.5 mhz 0.45 v v in v cc 10 m a i lo output leakage current @ 0.5 mhz 0.45 v v out v cc (c) 10 m a v clo clock output low i clo = 4.0 ma 0.45 v v cho clock output high i cho = C500 m av cc C0.5 v
54 am186/188es and am186/188eslv microcontrollers preliminary capacitance note: capacitance limits are guaranteed by characterization. power supply current for the following typical system specification shown in figure 11, i cc has been measured at 4.0 ma per mhz of system clock. for the following typical system specification shown in figure 12, i cc has been measured at 5.9 ma per mhz of system clock. the typical system is measured while the system is executing code in a typical application with maximum voltage and maximum case temperature. actual power supply current is dependent on system design and may be greater or less than the typical i cc figure presented here. typical current in figure 11 is given by: i cc = 4.0 ma freq(mhz) typical current in figure 12 is given by: i cc = 5.9 ma freq(mhz) please note that dynamic i cc measurements are de- pendent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the out- puts. for these i cc measurements, the devices were set to the following modes: n no dc loads on the output buffers n output capacitive load set to 35 pf n ad bus set to data only n pios are disabled n timer, serial port, refresh, and dma are enabled table 9 shows the variables that are used to calculate the typical power consumption value for each version of the am186eslv and am188eslv microcontrollers. table 9. typical power consumption calculation for the am186eslv and am188eslv figure 11. typical i cc versus frequency for the am186eslv and am188eslv figure 12. typical i cc versus frequency for am186es and am188es preliminary symbol parameter description test conditions min max unit c in input capacitance @ 1 mhz 10 pf c io output or i/o capacitance @ 1 mhz 20 pf mhz i cc volts / 1000 = p typical power in watts mhz typical i cc volts 20 4.0 3.6 0.288 25 4.0 3.6 0.360 clock frequency (mhz) i cc (ma) 25 mhz 20 mhz 0 20 40 60 80 100 120 140 10 20 30 clock frequency (mhz) i cc (ma) 25 mhz 33 mhz 20 mhz 40 mhz 0 40 80 120 160 200 240 280 10 20 30 40 50
am186/188es and am186/188eslv microcontrollers 55 preliminary thermal characteristics tqfp package the am186es and am188es microcontrollers are specified for operation with case temperature ranges from 0 c to +100 c for a commercial device. case temperature is measured at the top center of the package as shown in figure 13. the various temperatures and thermal resistances can be determined using the equations in figure 14 with information given in table 10. q ja is the total thermal resistance. q ja is the sum of q jc , the internal thermal resistance of the assembly, and q ca , the case to ambient thermal resistance. the variable p is power in watts. typical power supply current (i cc) is tbd ma per mhz of clock frequency. figure 13. thermal resistance( c/watt) figure 14. thermal characteristics equations table 10. thermal characteristics ( c/watt) q ja q ca q jc q ja = q jc + q ca t c package/board airflow (linear feet per minute) q ja q jc q ca pqfp/2-layer 0 fpm 45 7 38 200 fpm 39 7 32 400 fpm 35 7 28 600 fpm 33 7 26 tqfp/2-layer 0 fpm 56 10 46 200 fpm 461036 400 fpm 401030 600 fpm 381028 pqfp/4-layer to 6-layer 0 fpm 23518 200 fpm 21 5 16 400 fpm 19 5 14 600 fpm 17 5 12 tqfp/4-layer to 6-layer 0 fpm 30624 200 fpm 28 6 22 400 fpm 26 6 20 600 fpm 24 6 18 q ja = q jc + q ca p=i cc freq (mhz) v cc t j =t c +( p q jc ) t j =t a + ( p q ja ) t c =t j C( p q jc ) t c =t a +( p q ca ) t a =t j C( p q ja ) t a =t c C( p q ca )
56 am186/188es and am186/188eslv microcontrollers preliminary typical ambient temperatures the typical ambient temperature specifications are based on the following assumptions and calculations: the commercial operating range of the am186es and am188es microcontrollers is a case temperature t c of 0 to 100 degrees centigrade. t c is measured at the top center of the package. an increase in the ambient temperature causes a proportional increase in t c . the 40-mhz microcontroller is specified as 5.0 v plus or minus 5%. therefore, 5.25 v is used for calculating typical power consumption on the 40-mhz microcontroller. microcontrollers up to 33 mhz are specified as 5.0 v plus or minus 10%. therefore, 5.5 v is used for calculating typical power consumption up to 33 mhz. typical power supply current (i cc ) in normal usage is estimated at 5.9 ma per mhz of microcontroller clock rate. typical power consumption (watts) = (5.9 ma/mhz) times microcontroller clock rate times voltage divided by 1000. table 11 shows the variables that are used to calculate the typical power consumption value for each version of the am186es and am188es microcontrollers. table 11. typical power consumption calculation thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. a safe operating range for the device can be calculated using the formulas from figure 14 and the variables in table 10. by using the maximum case rating t c , the typical power consumption value from table 11, and q jc from table 10, the junction temperature t j can be calculated by using the following formula from figure 14. t j = t c + (p q jc ) table 12 shows t j values for the various versions of the am186es and am188es microcontrollers. the column titled speed/pkg/board in table 12 indicates the clock speed in mhz, the type of package (p for pqfp and t for tqfp), and the type of board (2 for 2- layer and 4-6 for 4-layer to 6-layer). table 12. junction temperature calculation by using t j from table 12, the typical power consumption value from table 11, and a q ja value from table 10, the typical ambient temperature t a can be calculated using the following formula from figure 14: t a = t j C (p q ja ) for example, t a for a 40-mhz pqfp design with a 2- layer board and 0 fpm airflow is calculated as follows: t a = 108.673 C (1.239 45) t a = 52.918 in this calculation, t j comes from table 12, p comes from table 11, and q ja comes from table 10. see table 13. t a for a 33-mhz tqfp design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: t a = 106.4251 C (1.07085 28) t a = 76.4413 see table 16 for the result of this calculation. table 13 through table 16 and figure 15 through figure 18 show t a based on the preceding assumptions and calculations for a range of q ja values with airflow from 0 linear feet per minute to 600 linear feet per minute. p = mhz i cc volts / 1000 typical power (p) in watts mhz typical i cc volts 40 5.9 5.25 1.239 33 5.9 5.5 1.07085 25 5.9 5.5 0.81125 20 5.9 5.5 0.649 speed/ pkg/ board t j t j = t c + (p q jc ) t c p q jc 40/p2 108.673 100 1.239 7 40/t2 112.39 100 1.239 10 40/p4-6 106.195 100 1.239 5 40/t4-6 107.434 100 1.239 6 33/p2 107.49595 100 1.07085 7 33/t2 110.7085 100 1.07085 10 33/p4-6 105.35425 100 1.07085 5 33/t4-6 106.4251 100 1.07085 6 25/p2 105.67875 100 0.81125 7 25/t2 108.1125 100 0.81125 10 25/p4-6 104.05625 100 0.81125 5 25/t4-6 104.8675 100 0.81125 6 20/p2 104.543 100 0.649 7 20/t2 106.49 100 0.649 10 20/p4-6 103.245 100 0.649 5 20/t4-6 103.894 100 0.649 6
am186/188es and am186/188eslv microcontrollers 57 preliminary table 13 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used on a 2- layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 15 graphically illustrates the typical temperatures in table 13. table 13. typical ambient temperatures for pqfp with a 2-layer board figure 15. typical ambient temperatures for pqfp with a 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 52.918 60.352 65.308 67.786 33 mhz 1.07085 59.3077 65.7328 70.0162 72.1579 25 mhz 0.81125 69.1725 74.04 77.285 78.9075 20 mhz 0.649 75.338 79.232 81.828 83.126 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 40 50 60 70 80 90 l l l l v v v v u u u u n n n n
58 am186/188es and am186/188eslv microcontrollers preliminary table 14 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used on a 2- layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 16 graphically illustrates the typical temperatures in table 14. table 14. typical ambient temperatures for tqfp with a 2-layer board figure 16. typical ambient temperatures for tqfp with a 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 43.006 55.396 62.83 65.308 33 mhz 1.07085 50.7409 61.4494 67.8745 70.0162 25 mhz 0.81125 62.6825 70.795 75.6625 77.285 20 mhz 0.649 70.146 76.636 80.53 81.828 airflow (linear feet per minute) l l l l v v v v u u u u n n n n 0 fpm 200 fpm 400 fpm 600 fpm l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 40 50 60 70 80 90 typical ambient temperature (degrees c)
am186/188es and am186/188eslv microcontrollers 59 preliminary table 15 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used on a 4- layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 17 graphically illustrates the typical temperatures in table 15. table 15. typical ambient temperatures for pqfp with a 4-layer to 6-layer board figure 17. typical ambient temperatures for pqfp with a 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 77.698 80.176 82.654 85.132 33 mhz 1.07085 80.7247 82.8664 85.0081 87.1498 25 mhz 0.81125 85.3975 87.02 88.6425 90.265 20 mhz 0.649 88.318 89.616 90.914 92.212 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 70 75 80 85 90 95 airflow (linear feet per minute) l l l l v v v v u u u u n n n n
60 am186/188es and am186/188eslv microcontrollers preliminary table 16 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used on a 4- layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 18 graphically illustrates the typical temperatures in table 16. table 16. typical ambient temperatures for tqfp with a 4-layer to 6-layer board figure 18. typical ambient temperatures for tqfp with a 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 70.264 72.742 75.22 77.698 33 mhz 1.07085 74.2996 76.4413 78.583 80.7247 25 mhz 0.81125 80.53 82.1525 83.775 85.3975 20 mhz 0.649 84.424 85.722 87.02 88.318 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) 70 75 80 85 90 95 l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: airflow (linear feet per minute) l l l l v v v v u u u u n n n n
am186/188es and am186/188eslv microcontrollers 61 preliminary commercial switching characteristics and waveforms in the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. these periods are referred to as time states. a typical bus cycle is composed of four consecutive time states: t 1 , t 2 , t 3 , and t 4 . wait states, which represent multiple t 3 states, are referred to as t w states. when no bus cycle is pending, an idle (t i ) state occurs. in the switching parameter descriptions, the multiplexed address is referred to as the ad address bus; the demultiplexed address is referred to as the a address bus. key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform input output invalid invalid
62 am186/188es and am186/188eslv microcontrollers preliminary alphabetical key to switching parameter symbols parameter symbol no. description t arych 49 ardy resolution transition setup time t arychl 51 ardy inactive holding time t aryhdsh 95 ardy high to ds high t aryhdv 89 ardy assert to data valid t arylcl 52 ardy setup time t aryldsh 96 ardy low to ds high t avbl 87 a address valid to whb , wlb low t avch 14 ad address valid to clock high t avll 12 ad address valid to ale low t avrl 66 a address valid to rd low t avwl 65 a address valid to wr low t azrl 24 ad address float to rd active t ch1ch2 45 clkouta rise time t chav 68 clkouta high to a address valid t chck 38 x1 high time t chcl 44 clkouta high time t chcsv 67 clkouta high to lcs /ucs valid t chcsx 18 mcs /pcs inactive delay t chctv 22 control active delay 2 t chcv 64 command lines valid delay (after float) t chcz 63 command lines float delay t chdx 8 status hold time t chlh 9 ale active delay t chll 11 ale inactive delay t chrfd 79 clkouta high to rfsh valid t chsv 3 status active delay t cicoa 69 x1 to clkouta skew t cicob 70 x1 to clkoutb skew t ckhl 39 x1 fall time t ckin 36 x1 period t cklh 40 x1 rise time t cl2cl1 46 clkouta fall time t clarx 50 ardy active hold time t clav 5 ad address valid delay t clax 6 address hold t claz 15 ad address float delay t clch 43 clkouta low time t clck 37 x1 low time t clcl 42 clkouta period t clclx 80 lcs inactive delay t clcsl 81 lcs active delay
am186/188es and am186/188eslv microcontrollers 63 preliminary alphabetical key to switching parameter symbols (continued) parameter symbol no. description t clcsv 16 mcs /pcs active delay t cldox 30 data hold time t cldv 7 data valid delay t cldx 2 data in hold t clhav 62 hlda valid delay t clrf 82 clkouta high to rfsh invalid t clrh 27 rd inactive delay t clrl 25 rd active delay t clsh 4 status inactive delay t clsry 48 srdy transition hold time t cltmv 55 timer output delay t coaob 83 clkouta to clkoutb skew t csharyl 88 chip select to ardy low t cvctv 20 control active delay 1 t cvctx 31 control inactive delay t cvdex 21 den inactive delay t cxcsx 17 mcs /pcs hold from command inactive t dshdir 92 ds high to data invalidread t dshdiw 98 ds high to data invalidwrite t dshdx 93 ds high to data bus turn-off time t dshlh 41 ds inactive to ale inactive t dsldd 90 ds low to data driven t dsldv 91 ds low to data valid t dvcl 1 data in setup t dvdsl 97 data valid to ds low t dxdl 19 den inactive to dt/r low t hvcl 58 hold setup t invch 53 peripheral setup time t invcl 54 drq setup time t lcrf 86 lcs inactive to rfsh active delay t lhav 23 ale high to address valid t lhll 10 ale width t llax 13 ad address hold from ale inactive t lock 61 maximum pll lock time t lrll 84 lcs precharge pulse width t resin 57 res setup time t rfcy 85 rfsh cycle time t rhav 29 rd inactive to ad address active t rhdx 59 rd high to data hold on ad bus t rhdz 94 rd high to data bus turn-off time t rhlh 28 rd inactive to ale high
64 am186/188es and am186/188eslv microcontrollers preliminary alphabetical key to switching parameter symbols (continued) note: the following parameters are not defined or used as this time: 56, 60, 71C78. parameter symbol no. description t rlrh 26 rd pulse width t srycl 47 srdy transition setup time t whdex 35 wr inactive to den inactive t whdx 34 data hold after wr t whlh 33 wr inactive to ale high t wlwh 32 wr pulse width
am186/188es and am186/188eslv microcontrollers 65 preliminary numerical key to switching parameter symbols no. parameter symbol description 1 t dvcl data in setup 2 t cldx data in hold 3 t chsv status active delay 4 t clsh status inactive delay 5 t clav ad address valid delay 6 t clax address hold 7 t cldv data valid delay 8 t chdx status hold time 9 t chlh ale active delay 10 t lhll ale width 11 t chll ale inactive delay 12 t avll ad address valid to ale low 13 t llax ad address hold from ale inactive 14 t avch ad address valid to clock high 15 t claz ad address float delay 16 t clcsv mcs /pcs active delay 17 t cxcsx mcs /pcs hold from command inactive 18 t chcsx mcs /pcs inactive delay 19 t dxdl den inactive to dt/r low 20 t cvctv control active delay 1 21 t cvdex den inactive delay 22 t chctv control active delay 2 23 t lhav ale high to address valid 24 t azrl ad address float to rd active 25 t clrl rd active delay 26 t rlrh rd pulse width 27 t clrh rd inactive delay 28 t rhlh rd inactive to ale high 29 t rhav rd inactive to ad address active 30 t cldox data hold time 31 t cvctx control inactive delay 32 t wlwh wr pulse width 33 t whlh wr inactive to ale high 34 t whdx data hold after wr 35 t whdex wr inactive to den inactive 36 t ckin x1 period 37 t clck x1 low time 38 t chck x1 high time 39 t ckhl x1 fall time 40 t cklh x1 rise time 41 t dshlh ds inactive to ale inactive 42 t clcl clkouta period
66 am186/188es and am186/188eslv microcontrollers preliminary numerical key to switching parameter symbols (continued) no. parameter symbol description 43 t clch clkouta low time 44 t chcl clkouta high time 45 t ch1ch2 clkouta rise time 46 t cl2cl1 clkouta fall time 47 t srycl srdy transition setup time 48 t clsry srdy transition hold time 49 t arych ardy resolution transition setup time 50 t clarx ardy active hold time 51 t arychl ardy inactive holding time 52 t arylcl ardy setup time 53 t invch peripheral setup time 54 t invcl drq setup time 55 t cltmv timer output delay 57 t resin res setup time 58 t hvcl hold setup 59 t rhdx rd high to data hold on ad bus 61 t lock maximum pll lock time 62 t clhav hlda valid delay 63 t chcz command lines float delay 64 t chcv command lines valid delay (after float) 65 t avwl a address valid to wr low 66 t avrl a address valid to rd low 67 t chcsv clkouta high to lcs /ucs valid 68 t chav clkouta high to a address valid 69 t cicoa x1 to clkouta skew 70 t cicob x1 to clkoutb skew 79 t chrfd clkouta high to rfsh valid 80 t clclx lcs inactive delay 81 t clcsl lcs active delay 82 t clrf clkouta high to rfsh invalid 83 t coaob clkouta to clkoutb skew 84 t lrll lcs precharge pulse width 85 t rfcy rfsh cycle time 86 t lcrf lcs inactive to rfsh active delay 87 t avbl a address valid to whb , wlb low 88 t csharyl chip select to ardy low 89 t aryhdv ardy assert to data valid 90 t dsldd ds low to data driven 91 t dsldv ds low to data valid 92 t dshdir ds high to data invalidread 93 t dshdx ds high to data bus turn-off time
am186/188es and am186/188eslv microcontrollers 67 preliminary numerical key to switching parameter symbols (continued) note: the following parameters are not defined or used as this time: 56, 60, 71C78. no. parameter symbol description 94 t rhdz rd high to data bus turn-off time 95 t aryhdsh ardy high to ds high 96 t aryldsh ardy low to ds high 97 t dvdsl data valid to ds low 98 t dshdiw ds high to data invalidwrite
68 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges read cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 10 10 ns 2t cldx data in hold (c) 33ns general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address valid delay and bhe 0 25 0 20 ns 6t clax address hold 025020ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10= 40 t clcl C10= 30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch l C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 025020ns 21 t cvdex den inactive delay 0 12 0 12 ns 22 t chctv control active delay 2 (b) 025020ns 23 t lhav ale high to address valid 20 15 ns 99 t plal pcs low to ale low 15 28 15 24 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15= 85 2t clcl C15= 65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 29 t rhav rd inactive to ad address active (a) t clcl C10= 40 t clcl C10= 30 ns 41 t dshlh ds inactive to ale high t clch C2= 21 t clch C2= 16 59 t rhdx rd high to data hold on ad bus (c) 00ns 66 t avrl a address valid to rd low (a) t clcl + t chcl C3 t clcl + t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid025020ns 68 t chav clkouta high to a address valid 025020ns
am186/188es and am186/188eslv microcontrollers 69 preliminary switching characteristics over commercial operating ranges read cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 8 5 ns 2t cldx data in hold (c) 32ns general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address valid delay and bhe 0 15 0 12 ns 6t clax address hold 015012ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015012ns 21 t cvdex den inactive delay 0 12 0 12 ns 22 t chctv control active delay 2 (b) 015012ns 23 t lhav ale high to address valid 10 7.5 ns 99 t plal pcs low to ale low 12 20 10 18 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15=45 2t clcl C10=40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C2 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=20 t clcl C5=20 ns 41 t dshlh ds inactive to ale inactive t clch C2=11.5 t clch C2=9.25 59 t rhdx rd high to data hold on ad bus (c) 00ns 66 t avrl a address valid to rd low (a) t clcl + t chcl C3 t clcl + t chcl C 1.125 ns 67 t chcsv clkouta high to lcs /ucs valid015010ns 68 t chav clkouta high to a address valid 015010ns
70 am186/188es and am186/188eslv microcontrollers preliminary read cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 lcs , ucs rd mcs 1Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 a19Ca0 den , ds dt/r s6/lock s6 bhe * ale 1 2 3 4 5 6 8 9 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 29 68 66 67 28 10 uzi ao15Cao8** notes: * am186es microcontroller only ** am188es microcontroller only *** changes in t phase preceding next bus cycle if followed by read, inta, or halt. 59 lock 23 ad15Cad0*, ad7Cad0** data address s6 status address address bhe *** *** 41 99
am186/188es and am186/188eslv microcontrollers 71 preliminary switching characteristics over commercial operating ranges write cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih = 2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address valid delay and bhe 0 25 0 20 ns 6t clax address hold 025020ns 7t cldv data valid delay 0 15 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015020ns 21 t cvdex ds inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 025020ns 32 t wlwh wr pulse width 2t clcl C10=90 2t clcl C10=70 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=40 t clcl C10=30 ns 35 t whdex wr inactive to den inactive (a) t clch C3 t clch C3 ns 41 t dshlh ds inactive to ale high t clch C2= 21 t clch C2= 16 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid025020ns 68 t chav clkouta high to a address valid 025020ns 87 t avbl a address valid to whb, wlb low t chcl C3 25 t chcl C3 20 ns 98 t dshdiw ds high to data invalidwrite 35 0 30 ns
72 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges write cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , ds , inta 1Cinta 0, wr , whb , and wlb signals. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address valid delay and bhe 0 15 0 12 ns 6t clax address hold 025020ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015012ns 21 t cvdex ds inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 015012ns 32 t wlwh wr pulse width 2t clcl C10=50 2t clcl C10=40 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=20 t clcl C10=15 ns 35 t whdex wr inactive to den inactive (a) t clch C5 t clch ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C 1.25 ns 67 t chcsv clkouta high to lcs /ucs valid015010ns 68 t chav clkouta high to a address valid 015010ns 87 t avbl a address valid to whb, wlb low t chcl C3 15 t chcl C1.25 12 ns 98 t dshdiw ds high to data invalidwrite 0 20 0 15 ns
am186/188es and am186/188eslv microcontrollers 73 preliminary write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status lcs , ucs address data ad15Cad0*, ad7Cad0** wr mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 a19Ca0 den dt/r s6/lock s6 ale whb *, wlb * wb ** bhe * 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 67 68 65 35 31 20 30 34 32 31 33 uzi s6 20 31 87 ao15Cao8** notes: * am186es microcontroller only ** am188es microcontroller only *** changes in t phase preceding next bus cycle if followed by read, inta, or halt. lock 23 ds 21 20 address address 6 bhe 41 20 98 22 22 *** *** 99
74 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges psram read cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C0.5 v. a testing is performed with equal loading on referenced pins. b if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 10 10 ns 2t cldx data in hold (b) 33ns general timing responses 5t clav ad address valid delay and bhe 0 25 0 20 ns 7t cldv data valid delay 0 25 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 23 t lhav ale high to address valid 20 15 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C3 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15=85 2t clcl C15=65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 59 t rhdx rd high to data hold on ad bus (b) 00ns 66 t avrl a address valid to rd low t clcl + t chcl C3 t clcl + t chcl C3 ns 68 t chav clkouta high to a address valid 025020ns
am186/188es and am186/188eslv microcontrollers 75 preliminary switching characteristics over commercial operating ranges psram read cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C0.5 v. a testing is performed with equal loading on referenced pins. b if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 8 5 ns 2t cldx data in hold (b) 32ns general timing responses 5t clav ad address valid delay and bhe 0 15 0 12 ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 23 t lhav ale high to address valid 10 7.5 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C 1.25 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15=45 2t clcl C10=40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C1.25 ns 59 t rhdx rd high to data hold on ad bus (b) 00ns 66 t avrl a address valid to rd low t clcl + t chcl C3 t clcl + t chcl C 1.25 ns 68 t chav clkouta high to a address valid 015010ns
76 am186/188es and am186/188eslv microcontrollers preliminary psram read cycle waveforms data clkouta t 1 t 2 t3 t w lcs address ad15Cad0*, ad7Cad0** rd a19Ca0 s6/lock ale 1 2 5 7 8 9 11 24 25 26 27 68 66 28 10 t4 81 84 t 1 address 80 80 27 ao15Cao8** notes: * am186es microcontroller only ** am188es microcontroller only 59 23 lock s6 address address s6
am186/188es and am186/188eslv microcontrollers 77 preliminary switching characteristics over commercial operating ranges psram write cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , wr , whb , and wlb signals. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 5t clav ad address valid delay and bhe 0 25 0 20 ns 7t cldv data valid delay 0 25 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C3 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 25 0 20 ns 32 t wlwh wr pulse width 2t clcl C10=90 2t clcl C10=70 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=40 t clcl C10=30 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns 87 t avbl a address valid to whb, wlb low t chcl C3 25 t chcl C3 20 ns
78 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges psram write cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , wr , whb , and wlb signals. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 5t clav ad address valid delay and bhe 0 15 0 12 ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 20 t cvctv control active delay 1 (b) 015012ns 23 t lhav ale high to address valid 10 7.5 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns 84 t lrll lcs precharge pulse width t clcl + t clch C 3 t clcl + t clch C 1.25 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 015012ns 32 t wlwh wr pulse width 2t clcl C10=50 2t clcl C10=40 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=20 t clcl C10=15 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C1.25 ns 68 t chav clkouta high to a address valid 015010ns 87 t avbl a address valid to whb , wlb low t chcl C3 15 t chcl C1.25 12 ns
am186/188es and am186/188eslv microcontrollers 79 preliminary psram write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w lcs data ad15Cad0*, ad7Cad0** wr address a19Ca0 s6/lock s6 ale whb *, wlb * wb ** 5 7 8 9 10 11 68 65 20 30 34 32 33 t 1 31 20 80 84 81 87 80 31 ao15Cao8** notes: * am186es microcontroller only ** am188es microcontroller only 23 lock address s6 address
80 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges psram refresh cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns read/write cycle timing responses 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15=85 2t clcl C15=65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 025020ns 82 t clrf clkouta high to rfsh invalid 025020ns 85 t rfcy rfsh cycle time 6 t clcl 6 t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C3 2t clcl C3
am186/188es and am186/188eslv microcontrollers 81 preliminary switching characteristics over commercial operating ranges psram refresh cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns read/write cycle timing responses 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15=45 2t clcl C10=40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C2 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 015012ns 82 t clrf clkouta high to rfsh invalid 015012ns 85 t rfcy rfsh cycle time 6 t clcl 6 t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C3 2t clcl C1.25
82 am186/188es and am186/188eslv microcontrollers preliminary psram refresh cycle waveforms clkouta t 1 t 2 t 3 t 4 t w * lcs rd address a19Ca0 ale 9 25 26 27 28 10 rfsh 11 t 1 79 85 82 80 81 86 * the period t w is fixed at 3 wait states for psram auto refresh only. 27 notes:
am186/188es and am186/188eslv microcontrollers 83 preliminary switching characteristics over commercial operating ranges interrupt acknowledge cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt /r signals. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 10 10 ns 2t cldx data in hold 3 3 ns general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 7t cldv data valid delay 0 25 0 20 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 025020ns 21 t cvdex den inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 (c) 025020ns 23 t lhav ale high to address valid 20 15 ns 31 t cvctx control inactive delay (b) 025020ns 68 t chav clkouta high to a address valid 025020ns
84 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges interrupt acknowledge cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt /r signals. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing requirements 1t dvcl data in setup 8 5 ns 2t cldx data in hold 3 2 ns general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 7t cldv data valid delay 0 15 0 12 ns 8t chdx status hold time 0 0 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 20 t cvctv control active delay 1 (b) 015012ns 21 t cvdex den inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 (c) 015012ns 23 t lhav ale high to address valid 10 7.5 ns 31 t cvctx control inactive delay (b) 015012ns 68 t chav clkouta high to a address valid 015010ns
am186/188es and am186/188eslv microcontrollers 85 preliminary interrupt acknowledge cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status ale ad15Cad0*, ad7Cad0** inta 1Cinta 0 den dt/r ptr a19Ca0 s6/lock bhe * bhe 8 1 2 3 4 7 9 10 11 12 15 19 20 22 22 22 68 31 (a) (b) (c) (d) s6 21 notes: * am186es microcontroller only ** am188es microcontroller only a the status bits become inactive in the state preceding t 4 . b the data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to t cldx (min). c this parameter applies for an interrupt acknowledge cycle that follows a write cycle. d if followed by a write cycle, this change occurs in the state preceding that write cycle. ao15Cao8** 4 lock 23 address address s6
86 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges software halt cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 25 0 20 ns 4t clsh status inactive delay 0 25 0 20 ns 5t clav ad address invalid delay and bhe 0 25 0 20 ns 9t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 19 t dxdl den inactive to dt/r low (a) 00ns 22 t chctv control active delay 2 (b) 025020ns 68 t chav clkouta high to a address invalid 025020ns
am186/188es and am186/188eslv microcontrollers 87 preliminary switching characteristics over commercial operating ranges software halt cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max general timing responses 3t chsv status active delay 0 15 0 12 ns 4t clsh status inactive delay 0 15 0 12 ns 5t clav ad address invalid delay and bhe 0 15 0 12 ns 9t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 19 t dxdl den inactive to dt/r low (a) 00ns 22 t chctv control active delay 2 (b) 015012ns 68 t chav clkouta high to a address invalid 015010ns
88 am186/188es and am186/188eslv microcontrollers preliminary software halt cycle waveforms clkouta t 1 t 2 t i t i s 2Cs 0 status ale invalid address s6, ad15Cad0*, ad7Cad0**, ao15Cao8** den dt/r invalid address a19Ca0 3 4 5 9 10 11 19 22 68 notes: * am186es microcontroller only ** am188es microcontroller only
am186/188es and am186/188eslv microcontrollers 89 preliminary switching characteristics over commercial operating ranges clock (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max clkin requirements 36 t ckin x1 period (a) 50 60 40 60 ns 37 t clck x1 low time (1.5 v) (a) 15 15 ns 38 t chck x1 high time (1.5 v) (a) 15 15 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 55ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 55ns clkout timing 42 t clcl clkouta period 50 40 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C2=23 0.5t clcl C2=18 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C2=23 0.5t clcl C2=18 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 33ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 33ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 25 25 ns
90 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges clock (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max clkin requirements 36 t ckin x1 period (a) 30 60 25 60 ns 37 t clck x1 low time (1.5 v) (a) 10 7.5 ns 38 t chck x1 high time (1.5 v) (a) 10 7.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 55ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 55ns clkout timing 42 t clcl clkouta period 30 25 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 33ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 33ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 25 25 ns
am186/188es and am186/188eslv microcontrollers 91 preliminary clock waveformsactive mode clock waveformspower-save mode x1 x2 clkoutb clkouta (active, f=000) 36 37 39 40 42 43 46 69 70 38 44 45 x1 clkouta (power-save, f=010) x2 clkoutb (like clkouta, cbf=0) clkoutb (like x1, cbf=1)
92 am186/188es and am186/188eslv microcontrollers preliminary switching characteristics over commercial operating ranges ready and peripheral (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. parameter preliminary preliminary unit 20 mhz 25 mhz no. symbol description min max min max ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 10 10 ns 48 t clsry srdy transition hold time (a) 33ns 49 t arych ardy resolution transition setup time (b) 10 10 ns 50 t clarx ardy active hold time (a) 44ns 51 t arychl ardy inactive holding time 6 6 ns 52 t arylcl ardy setup time (a) 15 15 ns 53 t invch peripheral setup time (b) 10 10 ns 54 t invcl drq setup time (b) 10 10 ns peripheral timing responses 55 t cltmv timer output delay 25 20 ns
am186/188es and am186/188eslv microcontrollers 93 preliminary switching characteristics over commercial operating ranges ready and peripheral (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. synchronous ready waveforms parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 85ns 48 t clsry srdy transition hold time (a) 32ns 49 t arych ardy resolution transition setup time (b) 85ns 50 t clarx ardy active hold time (a) 43ns 51 t arychl ardy inactive holding time 6 5 ns 52 t arylcl ardy setup time (a) 10 5 ns 53 t invch peripheral setup time (b) 85ns 54 t invcl drq setup time (b) 85ns peripheral timing responses 55 t cltmv timer output delay 15 12 ns clkouta t w t w t w t 4 srdy t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 47 48 case 1
94 am186/188es and am186/188eslv microcontrollers preliminary asynchronous ready waveforms peripheral waveforms clkouta t w t w t w t 4 ardy (normally not- ready system) t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 ardy (normally ready system) 49 50 49 51 50 52 case 1 clkouta tmrout1C tmrout0 drq1Cdrq0 int4Cint0, nmi, tmrin1Ctmrin0 53 54 55
am186/188es and am186/188eslv microcontrollers 95 preliminary switching characteristics over commercial operating ranges reset and bus hold (20 mhz and 25 mhz) reset and bus hold (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.45 v and v ih =2.4 v, except at x1 where v ih =v cc C 0.5 v. a this timing must be met to guarantee recognition at the next clock. parameter preliminary unit 20 mhz 25 mhz no. symbol description min max min max reset and bus hold timing requirements 5t clav ad address valid delay and bhe 0 25 0 20 ns 15 t claz ad address float delay 0 25 0 20 ns 57 t resin res setup time 10 10 ns 58 t hvcl hold setup (a) 10 10 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 25 0 20 ns 63 t chcz command lines float delay 25 20 ns 64 t chcv command lines valid delay (after float) 25 20 ns parameter preliminary unit 33 mhz 40 mhz no. symbol description min max min max reset and bus hold timing requirements 5t clav ad address valid delay and bhe 0 15 0 12 ns 15 t claz ad address float delay 0 15 0 12 ns 57 t resin res setup time 8 5 ns 58 t hvcl hold setup (a) 85ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 15 0 12 ns 63 t chcz command lines float delay 15 12 ns 64 t chcv command lines valid delay (after float) 15 12 ns
96 am186/188es and am186/188eslv microcontrollers preliminary reset waveforms signals related to reset waveforms x1 res clkouta 57 57 res clkouta bhe /aden , rfsh 2/aden , s6/clkdiv 2, and uzi ad15Cad0 (186) ao15Cao8, ad7Cad0 (188) three-state three-state
am186/188es and am186/188eslv microcontrollers 97 preliminary bus hold waveformsentering bus hold waveformsleaving clkouta t i t i t i ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t 4 t i t i case 2 58 62 15 63 case 1 clkouta t i t i t 1 ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t i t 4 t 1 case 2 t i t i 58 62 64 5 case 1
98 am186/188es and am186/188eslv microcontrollers preliminary tqfp physical dimensions pql 100, trimmed and formed thin quad flat pack pin 100 pin 25 pin 1 id 12.00 ref notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. pql100 4-15-94 C b C C a C C d C pin 75 12.00 ref 13.80 14.20 15.80 16.20 pin 50 13.80 14.20 15.80 16.20 C a C C c C s s1.60 max 0.50 basic 1.00 ref 1.35 1.45 see detail x seating plane top view side view
am186/188es and am186/188eslv microcontrollers 99 preliminary pql 100 (continued) 0.17 0.27 0.05 0.15 seating plane detail x 0.17 0.27 0 C7 gage plane 0.20 0.45 0.75 0.13 0.20 0 min 0.25 0.14 0.18 section s-s 1.60 max notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. pql100 4-15-94 max 0.08 lead coplanarity r
100 am186/188es and am186/188eslv microcontrollers preliminary pqfp physical dimensions pqr 100, trimmed and formed plastic quad flat pack notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. 17.00 17.40 13.90 14.10 12.35 ref pin 80 pin 100 pin 30 pin 50 pin 1 i.d. 19.90 20.10 see detail x seating plane 0.65 basic 0.25 min 2.70 2.90 3.35 max s s CaC CdC CbC CaC CcC top view side view 18.85 ref 23.00 23.40 pqr100 4-15-94
am186/188es and am186/188eslv microcontrollers 101 preliminary pqfp pqr 100 (continued) 0.20 min. flat shoulder 7 typ. 0 min. 0.30 0.05 r gage plane 0.25 0.73 1.03 0 -7 7 typ. detail x 0.22 0.38 0.15 0.23 3.35 max section s-s 0.15 0.23 0.22 0.38 note: not to scale; for reference only. pqr100 4-15-94 trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks of advanced micro devices, inc. am186, am188, e86, k86, lan, and amd facts-on-demand are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
102 am186/188es and am186/188eslv microcontrollers preliminary

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